add sv.divmod2du test, inverse of the sv.madded

[openpower-isa.git] / src / openpower / test / runner.py

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 02b78b93950af3b16a0f0450bee2f1d9152afc9a..cf9b28b3615bae44be508337fc6e3adfe0e92beb 100644 (file)
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -48,8 +48,10 @@ class SimRunner(StateRunner):
         self.dut = dut
 
         self.mmu = pspec.mmu == True
+        fp_en = pspec.fp_en == True
         regreduce_en = pspec.regreduce_en == True
-        self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
+        self.simdec2 = simdec2 = PowerDecode2(
+            None, regreduce_en=regreduce_en, fp_en=fp_en)
         m.submodules.simdec2 = simdec2  # pain in the neck
 
     def prepare_for_test(self, test):
@@ -71,17 +73,22 @@ class SimRunner(StateRunner):
                   disassembly=insncode,
                   bigendian=bigendian,
                   initial_svstate=test.svstate,
-                  mmu=self.mmu)
+                  mmu=self.mmu,
+                  fpregfile=test.fpregs)
 
         # run the loop of the instructions on the current test
         index = sim.pc.CIA.value//4
         while index < len(instructions):
             ins, code = instructions[index]
 
-            log("sim instr: 0x{:X} pc=0x{:X}".format(ins & 0xffffffff,
-                                                     sim.pc.CIA.value),
+            # extra new-line so it's easier to visually separate each
+            # instruction in output
+            log(f"\n0x{sim.pc.CIA.value:04X}: {ins % (1 << 32):08X} {code}",
                 kind=LogKind.InstrInOuts)
-            log(index, code, kind=LogKind.InstrInOuts)
+
+            log("sim instr: 0x{:X} pc=0x{:X}".format(ins & 0xffffffff,
+                                                     sim.pc.CIA.value))
+            log(index, code)
 
             # set up simulated instruction (in simdec2)
             try:
@@ -91,7 +98,7 @@ class SimRunner(StateRunner):
             yield Settle()
 
             # call simulated operation
-            log("sim", code, kind=LogKind.InstrInOuts)
+            log("sim", code)
             yield from sim.execute_one()
             yield Settle()
             index = sim.pc.CIA.value//4
@@ -123,7 +130,7 @@ class TestRunnerBase(FHDLTestCase):
 
     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
                  svp64=True, run_hdl=None, run_sim=True,
-                 allow_overlap=False, inorder=False):
+                 allow_overlap=False, inorder=False, fp=False):
         super().__init__("run_all")
         self.test_data = tst_data
         self.microwatt_mmu = microwatt_mmu
@@ -133,6 +140,7 @@ class TestRunnerBase(FHDLTestCase):
         self.inorder = inorder
         self.run_hdl = run_hdl
         self.run_sim = run_sim
+        self.fp = fp
 
     def run_all(self):
         m = Module()
@@ -166,7 +174,8 @@ class TestRunnerBase(FHDLTestCase):
                      allow_overlap=self.allow_overlap,
                      inorder=self.inorder,
                      mmu=self.microwatt_mmu,
-                     reg_wid=64)
+                     reg_wid=64,
+                     fp_en=self.fp)
 
         ###### SETUP PHASE #######
         # Determine the simulations needed and add to state_list
@@ -228,14 +237,43 @@ class TestRunnerBase(FHDLTestCase):
                     for runner in state_list:
                         yield from runner.prepare_for_test(test)
 
-                    log("running test: ", test.name, kind=LogKind.InstrInOuts)
+                    log("running test: ", test.name, test.subtest_args,
+                        kind=LogKind.InstrInOuts)
                     program = test.program
-                    log("regs", test.regs, kind=LogKind.InstrInOuts)
+
+                    def format_regs(regs):
+                        # type: (list[int]) -> str
+                        out = []
+                        for i, v in enumerate(regs):
+                            values = ""
+                            for sz in (32, 64):
+                                for signed in ("u", "i"):
+                                    value = v % (1 << sz)
+                                    if signed == "i" and \
+                                            value & (1 << (sz - 1)) != 0:
+                                        value -= 1 << sz
+                                    values += f" {signed}{sz}:{value}"
+                            out.append(f"r{i} = 0x{v:X} {values}")
+                        return "\n".join(out)
+                    log("regs:", format_regs(test.regs),
+                        kind=LogKind.InstrInOuts)
                     log("sprs", test.sprs, kind=LogKind.InstrInOuts)
                     log("cr", test.cr, kind=LogKind.InstrInOuts)
-                    log("mem", test.mem, kind=LogKind.InstrInOuts)
+                    log("mem", test.mem)
                     log("msr", test.msr, kind=LogKind.InstrInOuts)
-                    log("assem", program.assembly, kind=LogKind.InstrInOuts)
+
+                    def format_assembly(assembly):
+                        # type: (str) -> str
+                        pc = 0
+                        out = []
+                        for line in assembly.splitlines():
+                            out.append(f"pc=0x{pc:04X}: {line}")
+                            if not line.startswith(".set ") and \
+                                    line.partition('#')[0].strip() != "":
+                                pc += 4
+                        return "\n".join(out)
+                    log("assembly:\n" + format_assembly(program.assembly),
+                        kind=LogKind.InstrInOuts)
                     gen = list(program.generate_instructions())
                     insncode = program.assembly.splitlines()
                     instructions = list(zip(gen, insncode))