"""
from nmigen import Module, ClockSignal
-from copy import copy
+from copy import copy, deepcopy
+from pprint import pprint
# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
# Also, check out the cxxsim nmigen branch, and latest yosys from git
from soc.config.test.test_loadstore import TestMemPspec
from nmutil.util import wrap
from openpower.test.wb_get import wb_get
+import openpower.test.wb_get as wbget
from openpower.test.state import TestState, StateRunner, ExpectedState
"""
def __init__(self, tst_data, microwatt_mmu=False, rom=None,
svp64=True, run_hdl=None, run_sim=True,
- allow_overlap=False):
+ allow_overlap=False, inorder=False):
super().__init__("run_all")
self.test_data = tst_data
self.microwatt_mmu = microwatt_mmu
self.rom = rom
self.svp64 = svp64
self.allow_overlap = allow_overlap
+ self.inorder = inorder
self.run_hdl = run_hdl
self.run_sim = run_sim
m = Module()
comb = m.d.comb
if self.microwatt_mmu:
- ldst_ifacetype = 'test_mmu_cache_wb'
+ # do not wire these up to anything if wb_get is to be used
+ if self.rom is not None:
+ ldst_ifacetype = 'mmu_cache_wb'
+ imem_ifacetype = 'mmu_cache_wb'
+ else:
+ ldst_ifacetype = 'test_mmu_cache_wb'
+ imem_ifacetype = 'test_bare_wb'
else:
ldst_ifacetype = 'test_bare_wb'
- imem_ifacetype = 'test_bare_wb'
+ imem_ifacetype = 'test_bare_wb'
pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
imem_ifacetype=imem_ifacetype,
- addr_wid=48,
+ addr_wid=64,
mask_wid=8,
imem_reg_wid=64,
# wb_data_width=32,
xics=False,
gpio=False,
regreduce=not self.allow_overlap,
+ core_domain="sync", # no alternative domain
svp64=self.svp64,
allow_overlap=self.allow_overlap,
+ inorder=self.inorder,
mmu=self.microwatt_mmu,
reg_wid=64)
# The methods contained in the respective Runner classes are
# called using this list when possible
+ # allow wb_get to run
+ if self.rom is not None:
+ wbget.stop = False
+
state_list = []
if self.run_hdl:
# but Simulation-only fails without it
intclk = ClockSignal("coresync")
comb += intclk.eq(ClockSignal())
+ dbgclk = ClockSignal("dbgsync")
+ comb += dbgclk.eq(ClockSignal())
# nmigen Simulation - everything runs around this, so it
# still has to be created.
###### PREPARATION PHASE AT START OF TEST #######
+ # HACK: if there is test memory and wb_get is in use,
+ # overwrite (reset) the wb_get memory dictionary with
+ # the test's memory contents (oh, and put the wb_get
+ # memory back in as well)
+ self.default_mem.clear()
+ if self.rom is not None:
+ self.default_mem.update(deepcopy(self.rom))
+ if test.mem is not None:
+ self.default_mem.update(deepcopy(test.mem))
+
for runner in state_list:
yield from runner.prepare_for_test(test)
# do actual comparison, against last item
last_sim.compare(test.expected)
+ # check number of instructions run (sanity)
if self.run_hdl and self.run_sim:
- self.assertTrue(len(hdl_states) == len(sim_states),
- "number of instructions run not the same")
+ n_hdl = len(hdl_states)
+ n_sim = len(sim_states)
+ self.assertTrue(n_hdl == n_sim,
+ "number of instructions %d %d "
+ "run not the same" % (n_hdl, n_sim))
###### END OF A TEST #######
# StateRunner.end_test()
for runner in state_list:
yield from runner.cleanup() # TODO, some arguments?
+ # finally stop wb_get from going
+ if self.rom is not None:
+ wbget.stop = True
+
styles = {
'dec': {'base': 'dec'},
'bin': {'base': 'bin'},
if self.microwatt_mmu:
traces += [
{'comment': 'microwatt_mmu'},
- 'core.mmu0.illegal',
- 'core.mmu0.debug0[3:0]',
- 'core.mmu.state',
- 'core.mmu.pid[31:0]',
- 'core.mmu.prtbl[63:0]',
- 'core.state', # actually LoadStore1
+ 'core.fus.mmu0.alu_mmu0.illegal',
+ 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
+ 'core.fus.mmu0.alu_mmu0.mmu.state',
+ 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
+ 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
{'comment': 'wishbone_memory'},
- 'core.dcache.wb_in_ack',
- 'core.dcache.wb_in_stall,'
- 'core.dcache.wb_in_dat,'
- 'core.dcache.wb_out_cyc',
- 'core.dcache.wb_out_stb',
- 'core.dcache.wb_out_we',
- 'core.dcache.wb_out_adr',
- 'core.dcache.wb_out_dat',
- 'core.dcache.wb_out_sel',
+ 'core.l0.pimem.bus__ack',
+ 'core.l0.pimem.bus__adr[4:0]',
+ 'core.l0.pimem.bus__bte',
+ 'core.l0.pimem.bus__cti',
+ 'core.l0.pimem.bus__cyc',
+ 'core.l0.pimem.bus__dat_r[63:0]',
+ 'core.l0.pimem.bus__dat_w[63:0]',
+ 'core.l0.pimem.bus__dat_err',
+ 'core.l0.pimem.bus__dat_sel[7:0]',
+ 'core.l0.pimem.bus__dat_stb',
+ 'core.l0.pimem.bus__dat_we',
]
- write_gtkw("issuer_simulator.gtkw",
- "issuer_simulator.vcd",
+ gtkname = "issuer_simulator"
+ if self.rom:
+ gtkname += "_mmu"
+
+ write_gtkw("%s.gtkw" % gtkname,
+ "%s.vcd" % gtkname,
traces, styles, module='top.issuer')
# add run of instructions
# optionally, if a wishbone-based ROM is passed in, run that as an
# extra emulated process
+ self.default_mem = {}
if self.rom is not None:
+ print ("TestRunner with MMU ROM")
+ pprint (self.rom)
dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
- default_mem = self.rom
- sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
-
- with sim.write_vcd("issuer_simulator.vcd"):
+ icache = hdlrun.issuer.core.fus.fus["mmu0"].alu.icache
+ self.default_mem = deepcopy(self.rom)
+ sim.add_sync_process(wrap(wb_get(dcache.bus,
+ self.default_mem, "DCACHE")))
+ sim.add_sync_process(wrap(wb_get(icache.ibus,
+ self.default_mem, "ICACHE")))
+
+ with sim.write_vcd("%s.vcd" % gtkname):
sim.run()
projects / openpower-isa.git / blobdiff