`define SDR_INIT_DONE 8'h58
`define SDR_WIDTH 8'h60
`define SDR_COLBITS 8'h68
-`define SDR_SDIO_CTRL 8'h70
`define SDR_CLK_DELAY 8'h78
`define verbose
package sdr_top;
+import GetPut:: *;
import Semi_FIFOF :: *;
import AXI4_Types :: *;
import AXI4_Fabric :: *;
interface Get#(Bit#(8)) osdr_dqm;
interface Get#(Bit#(2)) osdr_ba;
interface Get#(Bit#(13)) osdr_addr;
+ interface Get#(Bit#(1)) osdr_clock;
endinterface
interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_sdram;
interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave_cntrl_reg;
interface Ifc_sdram_out ifc_sdram_out;
- method Bit#(9) sdram_sdio_ctrl;
- interface Clock sdram_clk;
endinterface
typedef enum{
(*synthesize*)
-module mksdr_axi4_slave#(Clock clk0) (Ifc_sdr_slave);
+module mksdr_axi4_slave#(Clock clk0, Reset rst0) (Ifc_sdr_slave);
- Reset rst0 <- mkAsyncResetFromCR (0, clk0);
-
Reg#(Bit#(9)) rg_delay_count <- mkReg(0,clocked_by clk0, reset_by rst0);
Reg#(Bit#(9)) rg_rd_actual_len <- mkReg(0,clocked_by clk0, reset_by rst0);
Reg#(bit) rg_app_req <- mkDReg(0,clocked_by clk0, reset_by rst0);
Reg#(Bit#(4)) rg_cfg_sdr_twr_d <- mkConfigReg(4'h1,clocked_by clk0, reset_by rst0);
Reg#(Bit#(2)) rg_cfg_sdr_width <- mkConfigReg(2'b0,clocked_by clk0, reset_by rst0);
Reg#(Bit#(2)) rg_cfg_colbits <- mkConfigReg(2'b01,clocked_by clk0, reset_by rst0);
- Reg#(Bit#(9)) rg_cfg_sdio_ctrl <- mkConfigReg(9'b000100011,clocked_by clk0, reset_by rst0);
Reg#(Bit#(8)) rg_cfg_sdr_clk_delay <- mkConfigReg(8'b00001000,clocked_by clk0, reset_by rst0);
Reg#(Bit#(`SDR_RFSH_TIMER_W )) rg_cfg_sdr_rfsh <- mkConfigReg(12'h100,clocked_by clk0, reset_by rst0);
AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor_cntrl_reg <- mkAXI4_Slave_Xactor;
Ifc_sdram sdr_cntrl <- mksdrc_top(clocked_by clk0, reset_by rst0);
+ // TODO remove the following when clock to bit type conversion is done
+ Reg#(Bit#(1)) rg_dummy <- mkReg(0, clocked_by clk0, reset_by rst0);
+
function Action fn_wr_cntrl_reg(Bit#(64) data, Bit#(8) address);
action
case(address)
`SDR_COLBITS : rg_cfg_colbits <= data [1:0];
- `SDR_SDIO_CTRL : rg_cfg_sdio_ctrl <= data [8:0];
`SDR_CLK_DELAY : rg_cfg_sdr_clk_delay <= data [7:0];
`SDR_COLBITS : return extend(rg_cfg_colbits);
- `SDR_SDIO_CTRL : return extend(rg_cfg_sdio_ctrl);
`SDR_CLK_DELAY : return extend(rg_cfg_sdr_clk_delay);
interface Ifc_sdram_out ifc_sdram_out;
interface ipad_sdr_din = interface Put
- method Action put(Bit#(64) in)
- sdr_cntrl.ipad_sdr_din <= in;
+ method Action put(Bit#(64) in);
+ sdr_cntrl.ipad_sdr_din(in);
endmethod
endinterface;
interface osdr_den_n = interface Get
method ActionValue#(Bit#(64)) get;
- Bit#(64) temp;
+ Bit#(64) temp = 0;
for (int i=0; i<8; i=i+1) begin
temp[i*8] = sdr_cntrl.osdr_den_n[i];
end
endmethod
endinterface;
+ interface osdr_clock = interface Get
+ method ActionValue#(Bit#(1)) get;
+ return rg_dummy;
+ endmethod
+ endinterface;
endinterface
- interface sdram_clk = clk0;
- method Bit#(9) sdram_sdio_ctrl();
- return rg_cfg_sdio_ctrl;
- endmethod
-
interface axi4_slave_sdram = s_xactor_sdram.axi_side;
interface axi4_slave_cntrl_reg = s_xactor_cntrl_reg.axi_side;