adding hyperram for arty a7 and also adding a workaround for some stupid issues

[ls2.git] / src / simsoctb.v

diff --git a/src/simsoctb.v b/src/simsoctb.v
index f51ed07d9c4cd5eec849b4f3fd7bfe0627125d7e..64fb39a1bf02f772acb8846c487cba04a4e78d16 100644 (file)
--- a/src/simsoctb.v
+++ b/src/simsoctb.v
@@ -51,7 +51,7 @@ module simsoctb;
     .ck(dram_ck),
     .ck_n(~dram_ck),
     .cke(dram_cke),
-    .cs_n(dram_cs_n),
+    .cs_n(~dram_cs_n),
     .ras_n(dram_ras_n),
     .cas_n(dram_cas_n),
     .we_n(dram_we_n),
@@ -69,7 +69,7 @@ module simsoctb;
 
   // uart, LEDs, switches
   wire uart_tx ;
-  wire uart_rx;
+  reg uart_rx = 0;
   wire led_0;
   wire led_1;
   wire led_2;