change sys/clk/rst to group together, add clock-select

[pinmux.git] / src / spec / pinfunctions.py

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index c046dbde379da882c5a17c381891a5df71e79f26..c26cc31e6564c4156d85be102c0db0a446265bbb 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -273,11 +273,8 @@ def vss(suffix, bank):
 def vdd(suffix, bank):
     return (RangePin("-"), [])
 
-def clk(suffix, bank):
-    return (RangePin("-"), [])
-
-def rst(suffix, bank):
-    return (RangePin("-"), [])
+def sys(suffix, bank):
+    return (['CLK-', 'RST-', 'PLLCLK-', 'PLLOUT+', 'CSEL0-', 'CSEL1-', 'CSEL2-'], [])
 
 # list functions by name here
 
@@ -303,8 +300,7 @@ pinspec = (('IIS', i2s),
            ('SDR', sdram3),
            ('VSS', vss),
            ('VDD', vdd),
-           ('CLK', clk),
-           ('RST', rst),
+           ('SYS', sys),
            ('EINT', eint),
            ('PWM', pwm),
            ('GPIO', gpio),