return emmc(suffix, bank, pincount=4)
-def nspi(suffix, bank, iosize):
- qpins = ['CK*', 'NSS*']
+def nspi(suffix, bank, iosize, masteronly=True):
+ if masteronly:
+ qpins = ['CK+', 'NSS+']
+ else:
+ qpins = ['CK*', 'NSS*']
inout = []
for i in range(iosize):
pname = "IO%d*" % i
inout.append(pname)
return (qpins, inout)
+
+def mspi(suffix, bank):
+ return nspi(suffix, bank, 2, masteronly=True)
+
+
+def mquadspi(suffix, bank):
+ return nspi(suffix, bank, 4, masteronly=True)
+
+
def spi(suffix, bank):
return nspi(suffix, bank, 2)
def jtag(suffix, bank):
- return (['TMS+', 'TDI-', 'TDO+', 'TCK+'], [])
+ return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
def uart(suffix, bank):
inout.append(pname)
for i in range(2):
buspins.append("CS%d+" % i)
- buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
- 'A0', 'A1', 'TS', 'TBST',
- 'TSIZ0', 'TSIZ1']
+ buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
+ # 'TS+', commented out for now, mirrors ALE, for mux'd mode
+ 'TBST+',
+ 'TSIZ0+', 'TSIZ1+']
for i in range(4):
- buspins.append("BWE%d" % i)
+ buspins.append("BWE%d+" % i)
for i in range(2, 6):
buspins.append("CS%d+" % i)
return (buspins, inout)
pinspec = (('IIS', i2s),
('MMC', emmc),
('SD', sdmmc),
+ ('MSPI', mspi),
+ ('MQSPI', mquadspi),
('SPI', spi),
('QSPI', quadspi),
('TWI', i2c),