return emmc(suffix, bank, pincount=4)
-def spi(suffix, bank):
- pins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
- return (pins, [])
-
-
-def quadspi(suffix, bank):
- qpins = ['CK*', 'NSS*']
+def nspi(suffix, bank, iosize, masteronly=True):
+ if masteronly:
+ qpins = ['CK+', 'NSS+']
+ else:
+ qpins = ['CK*', 'NSS*']
inout = []
- for i in range(4):
+ for i in range(iosize):
pname = "IO%d*" % i
qpins.append(pname)
inout.append(pname)
return (qpins, inout)
+def mspi(suffix, bank):
+ return nspi(suffix, bank, 2, masteronly=True)
+
+
+def mquadspi(suffix, bank):
+ return nspi(suffix, bank, 4, masteronly=True)
+
+
+def spi(suffix, bank):
+ return nspi(suffix, bank, 2)
+
+
+def quadspi(suffix, bank):
+ return nspi(suffix, bank, 4)
+
+
def i2c(suffix, bank):
return (['SDA*', 'SCL*'], [])
def jtag(suffix, bank):
- return (['TMS+', 'TDI-', 'TDO+', 'TCK+'], [])
+ return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [])
def uart(suffix, bank):
def rgbttl(suffix, bank):
ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
for i in range(24):
- ttlpins.append("D%d+" % i)
+ ttlpins.append("OUT%d+" % i)
return (ttlpins, [])
inout.append(pname)
for i in range(2):
buspins.append("CS%d+" % i)
- buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
- 'A0', 'A1', 'TS', 'TBST',
- 'TSIZ0', 'TSIZ1']
+ buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
+ # 'TS+', commented out for now, mirrors ALE, for mux'd mode
+ 'TBST+',
+ 'TSIZ0+', 'TSIZ1+']
for i in range(4):
- buspins.append("BWE%d" % i)
+ buspins.append("BWE%d+" % i)
for i in range(2, 6):
buspins.append("CS%d+" % i)
return (buspins, inout)
def sdram1(suffix, bank):
buspins = []
inout = []
- for i in range(16):
+ for i in range(8):
pname = "SDRDQM%d*" % i
buspins.append(pname)
+ for i in range(8):
+ pname = "SDRD%d*" % i
+ buspins.append(pname)
inout.append(pname)
for i in range(12):
buspins.append("SDRAD%d+" % i)
- for i in range(8):
- buspins.append("SDRDQ%d+" % i)
- for i in range(3):
- buspins.append("SDRCS%d#+" % i)
- for i in range(2):
- buspins.append("SDRDQ%d+" % i)
for i in range(2):
buspins.append("SDRBA%d+" % i)
- buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
- 'SDRRST+']
+ buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
+ 'SDRCSn0++']
return (buspins, inout)
def sdram2(suffix, bank):
buspins = []
inout = []
- for i in range(3, 6):
- buspins.append("SDRCS%d#+" % i)
- for i in range(16, 32):
+ for i in range(1, 6):
+ buspins.append("SDRCSn%d+" % i)
+ for i in range(8, 16):
pname = "SDRDQM%d*" % i
buspins.append(pname)
+ for i in range(8, 16):
+ pname = "SDRD%d*" % i
+ buspins.append(pname)
+ inout.append(pname)
+ return (buspins, inout)
+
+
+def sdram3(suffix, bank):
+ buspins = []
+ inout = []
+ for i in range(12, 13):
+ buspins.append("SDRAD%d+" % i)
+ for i in range(8, 64):
+ pname = "SDRD%d*" % i
+ buspins.append(pname)
inout.append(pname)
return (buspins, inout)
pinspec = (('IIS', i2s),
('MMC', emmc),
('SD', sdmmc),
+ ('MSPI', mspi),
+ ('MQSPI', mquadspi),
('SPI', spi),
('QSPI', quadspi),
('TWI', i2c),
('FB', flexbus2),
('SDR', sdram1),
('SDR', sdram2),
+ ('SDR', sdram3),
('EINT', eint),
('PWM', pwm),
('GPIO', gpio),