add not-connected pads to ls180

[pinmux.git] / src / spec / testing.py

diff --git a/src/spec/testing.py b/src/spec/testing.py
index 27a5b26a5bd77ba969df71c8f177f86fb5f256bb..14055af4e59ee4b75857acf6fa37071cbec5fde8 100644 (file)
--- a/src/spec/testing.py
+++ b/src/spec/testing.py
@@ -1,4 +1,7 @@
-from UserDict import UserDict
+try:
+    from UserDict import UserDict
+except ImportError:
+    from collections import UserDict
 
 
 class Wire(object):
@@ -27,9 +30,9 @@ class Wires(UserDict):
 
 
 def dummytest(ps, output_dir, output_type):
-    print ps, output_dir, output_type
-    print dir(ps)
-    print ps.fnspec
+    print (ps, output_dir, output_type)
+    print (dir(ps))
+    print (ps.fnspec)
 
     # basically we need to replicate the entirety of the
     # verilog module's inputs and outputs, so that we can