https://bitbucket.org/casl/pinmux.
Authors: Neel Gala, Luke
- Date of generation: Mon Jun 25 16:20:40 2018
+ Date of generation: Sun Jul 22 05:31:10 2018
*/
package pinmux;
endinterface
- interface PeripheralSide;
- // declare the interface to the peripherals
- // Each peripheral's function will be either an input, output
- // or be bi-directional. an input field will be an output from the
- // peripheral and an output field will be an input to the peripheral.
- // Bi-directional functions also have an output-enable (which
- // again comes *in* from the peripheral)
+ interface IOCellSide;
+ // declare the interface to the IO cells.
+ // Each IO cell will have 1 input field (output from pin mux)
+ // and an output and out-enable field (input to pinmux)
// interface declaration between IO-0 and pinmux
(*always_ready,always_enabled*) method Bit#(1) io0_cell_out;
(*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
endinterface
- interface IOCellSide;
- // declare the interface to the IO cells.
- // Each IO cell will have 1 input field (output from pin mux)
- // and an output and out-enable field (input to pinmux)
+ interface PeripheralSide;
+ // declare the interface to the peripherals
+ // Each peripheral's function will be either an input, output
+ // or be bi-directional. an input field will be an output from the
+ // peripheral and an output field will be an input to the peripheral.
+ // Bi-directional functions also have an output-enable (which
+ // again comes *in* from the peripheral)
// interface declaration between UART-0 and pinmux
(*always_ready,always_enabled*) method Action uart_tx (Bit#(1) in);
(*always_ready,always_enabled*) method Bit#(1) uart_rx;
/*====== This where the muxing starts for each io-cell======*/
+ Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
// output muxer for cell idx 0
cell0_mux_out=
wrcell0_mux==0?wrgpioa_a0_out:
- wrcell0_mux==1?wruart_tx_out:
- wrcell0_mux==2?0: // unused
- 0; // unused
+ wrcell0_mux==1?wruart_tx:
+ wrcell0_mux==2?val0: // unused
+ wrtwi_sda_out;
// outen muxer for cell idx 0
cell0_mux_outen=
wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional
- wrcell0_mux==1?1: // uart_tx is an output
- wrcell0_mux==2?0: // unused
- 0; // unused
+ wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output
+ wrcell0_mux==2?val0: // unused
+ wrtwi_sda_outen; // bi-directional
+ // priority-in-muxer for cell idx 0
rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0);
wrgpioa_a0_in<=cell0_mux_in;
endrule
+ rule assign_wrtwi_sda_in_on_cell0(wrcell0_mux==3);
+ wrtwi_sda_in<=cell0_mux_in;
+ endrule
+
// output muxer for cell idx 1
cell1_mux_out=
wrcell1_mux==0?wrgpioa_a1_out:
- wrcell1_mux==1?0: // uart_rx is an input
+ wrcell1_mux==1?val0: // uart_rx is an input
wrcell1_mux==2?wrtwi_sda_out:
- 0; // unused
+ val0; // unused
// outen muxer for cell idx 1
cell1_mux_outen=
wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional
- wrcell1_mux==1?0: // uart_rx is an input
+ wrcell1_mux==1?val0: // uart_rx is an input
wrcell1_mux==2?wrtwi_sda_outen: // bi-directional
- 0; // unused
+ val0; // unused
+ // priority-in-muxer for cell idx 1
rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0);
wrgpioa_a1_in<=cell1_mux_in;
endrule
-
rule assign_wruart_rx_on_cell1(wrcell1_mux==1);
wruart_rx<=cell1_mux_in;
endrule
-
rule assign_wrtwi_sda_in_on_cell1(wrcell1_mux==2);
wrtwi_sda_in<=cell1_mux_in;
endrule
// output muxer for cell idx 2
cell2_mux_out=
wrcell2_mux==0?wrgpioa_a2_out:
- wrcell2_mux==1?0: // unused
+ wrcell2_mux==1?val0: // unused
wrcell2_mux==2?wrtwi_scl_out:
- 0; // unused
+ val0; // unused
// outen muxer for cell idx 2
cell2_mux_outen=
wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional
- wrcell2_mux==1?0: // unused
+ wrcell2_mux==1?val0: // unused
wrcell2_mux==2?wrtwi_scl_outen: // bi-directional
- 0; // unused
+ val0; // unused
+ // priority-in-muxer for cell idx 2
rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
wrgpioa_a2_in<=cell2_mux_in;
endrule
-
rule assign_wrtwi_scl_in_on_cell2(wrcell2_mux==2);
wrtwi_scl_in<=cell2_mux_in;
endrule
+ /*=========================================*/
+ // dedicated cells
+
+
/*============================================================*/
interface mux_lines = interface MuxSelectionLines