test on hardware and clean up/fix

[litex.git] / targets / bist.py

diff --git a/targets/bist.py b/targets/bist.py
index f7ff733fbbae8b5a4ffc2a5d2a5016a53fc7c569..9d8031490dafaa4b4404ab9f82ced5e8b99a1d69 100644 (file)
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -1,4 +1,4 @@
-import os
+import os, atexit
 
 from litesata.common import *
 from migen.bank import csrgen
@@ -10,7 +10,10 @@ from migen.bank.description import *
 
 from misoclib import identifier
 
-from miscope import MiLa, Term, UART2Wishbone
+from litescope.common import *
+from litescope.bridge.uart2wb import LiteScopeUART2WB
+from litescope.frontend.la import LiteScopeLA
+from litescope.core.trigger import LiteScopeTerm
 
 from litesata.common import *
 from litesata.phy import LiteSATAPHY
@@ -18,7 +21,7 @@ from litesata import LiteSATA
 
 class _CRG(Module):
        def __init__(self, platform):
-               self.cd_sys = ClockDomain()
+               self.clock_domains.cd_sys = ClockDomain()
                self.reset = Signal()
 
                clk200 = platform.request("clk200")
@@ -56,23 +59,24 @@ class GenSoC(Module):
        csr_base = 0x00000000
        csr_data_width = 32
        csr_map = {
-               "uart2wb":                      0,
-               "identifier":           2,
+               "bridge":                       0,
+               "identifier":           1,
        }
        interrupt_map = {}
        cpu_type = None
        def __init__(self, platform, clk_freq):
+               self.clk_freq = clk_freq
                # UART <--> Wishbone bridge
-               self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)
+               self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
 
                # CSR bridge   0x00000000 (shadow @0x00000000)
-               self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
-               self._wb_masters = [self.uart2wb.wishbone]
+               self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
+               self._wb_masters = [self.bridge.wishbone]
                self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
                self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
 
                # CSR
-               self.identifier = identifier.Identifier(0, int(clk_freq), 0)
+               self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
 
        def add_cpu_memory_region(self, name, origin, length):
                self.cpu_memory_regions.append((name, origin, length))
@@ -82,14 +86,14 @@ class GenSoC(Module):
 
        def do_finalize(self):
                # Wishbone
-               self.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
+               self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
                        self._wb_slaves, register=True)
 
                # CSR
-               self.csrbankarray = csrgen.BankArray(self,
+               self.submodules.csrbankarray = csrgen.BankArray(self,
                        lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
                        data_width=self.csr_data_width)
-               self.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
+               self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
                for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
                        self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
                for name, memory, mapaddr, mmap in self.csrbankarray.srams:
@@ -132,27 +136,26 @@ class BISTSoC(GenSoC, AutoCSR):
                "sata":         10,
        }
        csr_map.update(GenSoC.csr_map)
-
-       def __init__(self, platform, export_mila=False):
+       def __init__(self, platform):
                clk_freq = 166*1000000
                GenSoC.__init__(self, platform, clk_freq)
-               self.crg = _CRG(platform)
+               self.submodules.crg = _CRG(platform)
 
                # SATA PHY/Core/Frontend
-               self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq)
+               self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
                self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
-               self.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True)
+               self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True)
 
                # Status Leds
-               self.leds = BISTLeds(platform, self.sata_phy)
+               self.submodules.leds = BISTLeds(platform, self.sata_phy)
 
 class BISTSoCDevel(BISTSoC, AutoCSR):
        csr_map = {
-               "mila":                 11
+               "la":                   20
        }
        csr_map.update(BISTSoC.csr_map)
-       def __init__(self, platform, export_mila=False):
-               BISTSoC.__init__(self, platform, export_mila)
+       def __init__(self, platform):
+               BISTSoC.__init__(self, platform)
 
                self.sata_core_link_rx_fsm_state = Signal(4)
                self.sata_core_link_tx_fsm_state = Signal(4)
@@ -161,7 +164,7 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
                self.sata_core_command_rx_fsm_state = Signal(4)
                self.sata_core_command_tx_fsm_state = Signal(4)
 
-               debug = (
+               self.debug = (
                        self.sata_phy.ctrl.ready,
 
                        self.sata_phy.source.stb,
@@ -198,11 +201,9 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
                        self.sata_core_command_tx_fsm_state,
                )
 
-               self.mila = MiLa(depth=2048, dat=Cat(*debug))
-               self.mila.add_port(Term)
-               if export_mila:
-                       mila_filename = os.path.join("test", "mila.csv")
-                       self.mila.export(self, debug, mila_filename)
+               self.submodules.la = LiteScopeLA(2048, self.debug)
+               self.la.add_port(LiteScopeTerm)
+               atexit.register(self.exit, platform)
 
        def do_finalize(self):
                BISTSoC.do_finalize(self)
@@ -215,4 +216,8 @@ class BISTSoCDevel(BISTSoC, AutoCSR):
                        self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state)
                ]
 
+       def exit(self, platform):
+               if platform.vns is not None:
+                       self.la.export(self.debug, platform.vns, "./test/la.csv")
+
 default_subtarget = BISTSoC