uart.c: rx overflow fix and tx simplification

[litex.git] / targets / simple.py

diff --git a/targets/simple.py b/targets/simple.py
index 095ab910a85ae6f2185ba94e78873e0f3febf949..3d2568483ac7f9b719ca33dc6cdcf05268ca8ac2 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -4,7 +4,7 @@ from migen.genlib.io import CRG
 
 from misoclib.soc import SoC, mem_decoder
 from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 
 class BaseSoC(SoC):
@@ -41,8 +41,8 @@ class MiniSoC(BaseSoC):
                                             platform.request("eth"))
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
                                             interface="wishbone",
-                                            with_hw_preamble_crc=False)
+                                            with_preamble_crc=False)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
 default_subtarget = BaseSoC