uart.c: rx overflow fix and tx simplification

[litex.git] / targets / simple.py

diff --git a/targets/simple.py b/targets/simple.py
index f03fa7cc826faf9087adbcbbc6a455fe43fad213..3d2568483ac7f9b719ca33dc6cdcf05268ca8ac2 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -1,46 +1,48 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone
-
-from misoclib import spiflash
-from misoclib.gensoc import GenSoC
-
-class PowerOnRst(Module):
-       def __init__(self, cd, overwrite_cd_rst=True):
-               self.clock_domains.cd_pwr_on = ClockDomain(reset_less=True)
-               self.cd_pwr_on.clk = cd.clk
-               self.pwr_on_rst = Signal()
-
-               rst_n = Signal()
-               self.sync.pwr_on += rst_n.eq(1)
-               self.comb += self.pwr_on_rst.eq(~rst_n)
-
-               if overwrite_cd_rst:
-                       self.comb += cd.rst.eq(self.pwr_on_rst)
-
-class SimpleSoC(GenSoC):
-       default_platform = "papilio_pro"
-
-       def __init__(self, platform, **kwargs):
-               GenSoC.__init__(self, platform,
-                       clk_freq=32*1000000,
-                       cpu_reset_address=0x60000,
-                       **kwargs)
-
-               # We can't use reset_less as CPU does require a reset signal
-               self.clock_domains.cd_sys = ClockDomain()
-               self.submodules += PowerOnRst(self.cd_sys)
-               self.comb += self.cd_sys.clk.eq(platform.request("clk32"))
-
-               # BIOS is in SPI flash
-               self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"),
-                       cmd=0xefef, cmd_width=16, addr_width=24, dummy=4)
-               self.flash_boot_address = 0x70000
-               self.register_rom(self.spiflash.bus)
-
-               # TODO: use on-board SDRAM instead of block RAM
-               sys_ram_size = 32*1024
-               self.submodules.sys_ram = wishbone.SRAM(sys_ram_size)
-               self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus)
-               self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)
-
-default_subtarget = SimpleSoC
+from migen.genlib.io import CRG
+
+from misoclib.soc import SoC, mem_decoder
+from misoclib.com.liteeth.phy import LiteEthPHY
+from misoclib.com.liteeth.core.mac import LiteEthMAC
+
+
+class BaseSoC(SoC):
+    def __init__(self, platform, **kwargs):
+        SoC.__init__(self, platform,
+            clk_freq=int((1/(platform.default_clk_period))*1000000000),
+            integrated_rom_size=0x8000,
+            integrated_main_ram_size=16*1024,
+            **kwargs)
+        self.submodules.crg = CRG(platform.request(platform.default_clk_name))
+
+
+class MiniSoC(BaseSoC):
+    csr_map = {
+        "ethphy": 20,
+        "ethmac": 21
+    }
+    csr_map.update(BaseSoC.csr_map)
+
+    interrupt_map = {
+        "ethmac": 2,
+    }
+    interrupt_map.update(BaseSoC.interrupt_map)
+
+    mem_map = {
+        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+    }
+    mem_map.update(BaseSoC.mem_map)
+
+    def __init__(self, platform, **kwargs):
+        BaseSoC.__init__(self, platform, **kwargs)
+
+        self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
+                                            platform.request("eth"))
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+                                            interface="wishbone",
+                                            with_preamble_crc=False)
+        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+
+default_subtarget = BaseSoC