bank/csrgen: interface -> bus

[litex.git] / top.py

diff --git a/top.py b/top.py
index 16bc91227f34cd890f844ee365d5476f8ddd6610..419ee9d0fd08a17b20529e31936a59d456667ee1 100644 (file)
--- a/top.py
+++ b/top.py
@@ -5,7 +5,7 @@ from migen.fhdl.structure import *
 from migen.fhdl import verilog, autofragment
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
 
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
+from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
        identifier, timer, minimac3, framebuffer, asmiprobe
 from cmacros import get_macros
 from constraints import Constraints
@@ -81,7 +81,7 @@ def get():
        #
        cpu0 = lm32.LM32()
        norflash0 = norflash.NorFlash(25, 12)
-       sram0 = sram.SRAM(sram_size//4)
+       sram0 = wishbone.SRAM(sram_size)
        minimac0 = minimac3.MiniMAC(csr_offset("MINIMAC"))
        wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
        wishbone2csr0 = wishbone2csr.WB2CSR()
@@ -97,14 +97,13 @@ def get():
                        cpu0.ibus,
                        cpu0.dbus
                ], [
-                       (binc("000"), norflash0.bus),
-                       (binc("001"), sram0.bus),
-                       (binc("011"), minimac0.membus),
-                       (binc("10"), wishbone2asmi0.wishbone),
-                       (binc("11"), wishbone2csr0.wishbone)
+                       (lambda a: a[26:29] == 0, norflash0.bus),
+                       (lambda a: a[26:29] == 1, sram0.bus),
+                       (lambda a: a[26:29] == 3, minimac0.membus),
+                       (lambda a: a[27:29] == 2, wishbone2asmi0.wishbone),
+                       (lambda a: a[27:29] == 3, wishbone2csr0.wishbone)
                ],
-               register=True,
-               offset=1)
+               register=True)
        
        #
        # CSR
@@ -115,13 +114,13 @@ def get():
        fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
        asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
        csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
-               uart0.bank.interface,
-               dfii0.bank.interface,
-               identifier0.bank.interface,
-               timer0.bank.interface,
-               minimac0.bank.interface,
-               fb0.bank.interface,
-               asmiprobe0.bank.interface
+               uart0.bank.bus,
+               dfii0.bank.bus,
+               identifier0.bank.bus,
+               timer0.bank.bus,
+               minimac0.bank.bus,
+               fb0.bank.bus,
+               asmiprobe0.bank.bus
        ])
        
        #