from migen.fhdl import verilog, autofragment
from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
- identifier, timer, minimac3, framebuffer
+from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
+ identifier, timer, minimac3, framebuffer, asmiprobe
from cmacros import get_macros
from constraints import Constraints
write_time=16
)
-def ddrphy_clocking(crg, phy):
- names = [
- "clk2x_270",
- "clk4x_wr",
- "clk4x_wr_strb",
- "clk4x_rd",
- "clk4x_rd_strb"
- ]
- comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
- return Fragment(comb)
-
csr_macros = get_macros("common/csrbase.h")
def csr_offset(name):
base = int(csr_macros[name + "_BASE"], 0)
#
cpu0 = lm32.LM32()
norflash0 = norflash.NorFlash(25, 12)
- sram0 = sram.SRAM(sram_size//4)
+ sram0 = wishbone.SRAM(sram_size)
minimac0 = minimac3.MiniMAC(csr_offset("MINIMAC"))
wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
wishbone2csr0 = wishbone2csr.WB2CSR()
cpu0.ibus,
cpu0.dbus
], [
- (binc("000"), norflash0.bus),
- (binc("001"), sram0.bus),
- (binc("011"), minimac0.membus),
- (binc("10"), wishbone2asmi0.wishbone),
- (binc("11"), wishbone2csr0.wishbone)
+ (lambda a: a[26:29] == 0, norflash0.bus),
+ (lambda a: a[26:29] == 1, sram0.bus),
+ (lambda a: a[26:29] == 3, minimac0.membus),
+ (lambda a: a[27:29] == 2, wishbone2asmi0.wishbone),
+ (lambda a: a[27:29] == 3, wishbone2csr0.wishbone)
],
- register=True,
- offset=1)
+ register=True)
#
# CSR
identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
timer0 = timer.Timer(csr_offset("TIMER0"))
fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
+ asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
- uart0.bank.interface,
- dfii0.bank.interface,
- identifier0.bank.interface,
- timer0.bank.interface,
- minimac0.bank.interface,
- fb0.bank.interface
+ uart0.bank.bus,
+ dfii0.bank.bus,
+ identifier0.bank.bus,
+ timer0.bank.bus,
+ minimac0.bank.bus,
+ fb0.bank.bus,
+ asmiprobe0.bank.bus
])
#
#
crg0 = m1crg.M1CRG(50*MHz, clk_freq)
- vga_clocking = Fragment([
- fb0.vga_clk.eq(crg0.vga_clk)
+ ddrphy_strobes = Fragment([
+ ddrphy0.clk4x_wr_strb.eq(crg0.clk4x_wr_strb),
+ ddrphy0.clk4x_rd_strb.eq(crg0.clk4x_rd_strb)
])
frag = autofragment.from_local() \
+ interrupts \
- + ddrphy_clocking(crg0, ddrphy0) \
- + vga_clocking
+ + ddrphy_strobes
cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0, fb0)
src_verilog, vns = verilog.convert(frag,
cst.get_ios(),
name="soc",
- clk_signal=crg0.sys_clk,
- rst_signal=crg0.sys_rst,
+ clock_domains={
+ "sys": crg0.cd_sys,
+ "sys2x_270": crg0.cd_sys2x_270,
+ "sys4x_wr": crg0.cd_sys4x_wr,
+ "sys4x_rd": crg0.cd_sys4x_rd,
+ "vga": crg0.cd_vga
+ },
return_ns=True)
src_ucf = cst.get_ucf(vns)
return (src_verilog, src_ucf)