Basic support for new clock domain and instance API

[litex.git] / top.py

diff --git a/top.py b/top.py
index a219234106e0947472addb89f3cb5fdcd4e2181b..621d76277a84b38076c39523717d3952708a6323 100644 (file)
--- a/top.py
+++ b/top.py
@@ -160,8 +160,7 @@ def get():
        src_verilog, vns = verilog.convert(frag,
                cst.get_ios(),
                name="soc",
-               clk_signal=crg0.sys_clk,
-               rst_signal=crg0.sys_rst,
+               clock_domains={"sys": crg0.cd_sys},
                return_ns=True)
        src_ucf = cst.get_ucf(vns)
        return (src_verilog, src_ucf)