asmicon/multiplexer: correct read-to-write delay to prevent conflicts on the tag bus

[litex.git] / top.py

diff --git a/top.py b/top.py
index 2a237960bed6e7d08dd301b2110c324258e3d23a..a219234106e0947472addb89f3cb5fdcd4e2181b 100644 (file)
--- a/top.py
+++ b/top.py
@@ -6,7 +6,7 @@ from migen.fhdl import verilog, autofragment
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
 
 from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
-       identifier, timer, minimac3, framebuffer
+       identifier, timer, minimac3, framebuffer, asmiprobe
 from cmacros import get_macros
 from constraints import Constraints
 
@@ -42,7 +42,6 @@ sdram_timing = asmicon.TimingSettings(
        CL=3,
        rd_delay=4,
 
-       slot_time=16,
        read_time=32,
        write_time=16
 )
@@ -125,13 +124,15 @@ def get():
        identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
        timer0 = timer.Timer(csr_offset("TIMER0"))
        fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
+       asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
        csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
                uart0.bank.interface,
                dfii0.bank.interface,
                identifier0.bank.interface,
                timer0.bank.interface,
                minimac0.bank.interface,
-               fb0.bank.interface
+               fb0.bank.interface,
+               asmiprobe0.bank.interface
        ])
        
        #