arch: Resurrect the NOISA build target and rename it NULL
authorAndreas Hansson <andreas.hansson@arm.com>
Wed, 4 Sep 2013 17:22:57 +0000 (13:22 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Wed, 4 Sep 2013 17:22:57 +0000 (13:22 -0400)
commit19a5b68db7d73542833d94ec8b23cad6daf0a787
tree589541b322580a54e539e24932d3b4bba05801db
parentea402970185d5df01dbad2c0f41b8d76d2eb01cd
arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
39 files changed:
build_opts/NOISA [deleted file]
build_opts/NULL [new file with mode: 0644]
src/arch/generic/SConscript
src/arch/noisa/SConsopts [deleted file]
src/arch/noisa/cpu_dummy.hh [deleted file]
src/arch/null/SConscript [new file with mode: 0644]
src/arch/null/SConsopts [new file with mode: 0644]
src/arch/null/cpu_dummy.cc [new file with mode: 0644]
src/arch/null/cpu_dummy.hh [new file with mode: 0644]
src/arch/null/isa_traits.hh [new file with mode: 0644]
src/arch/null/registers.hh [new file with mode: 0644]
src/arch/null/remote_gdb.hh [new file with mode: 0644]
src/arch/null/types.hh [new file with mode: 0644]
src/arch/null/utility.hh [new file with mode: 0644]
src/base/SConscript
src/cpu/SConscript
src/cpu/base.hh
src/cpu/intr_control_noisa.cc [new file with mode: 0644]
src/dev/SConscript
src/dev/sinic.cc
src/kern/SConscript
src/mem/SConscript
src/mem/cache/SConscript
src/mem/cache/base.cc
src/mem/cache/prefetch/SConscript
src/mem/cache/tags/SConscript
src/mem/cache/tags/base.cc
src/mem/fs_translating_port_proxy.cc
src/mem/fs_translating_port_proxy.hh
src/mem/port_proxy.hh
src/mem/ruby/SConscript
src/python/swig/pyobject.cc
src/sim/SConscript
src/sim/arguments.hh
src/sim/stat_control.cc
src/sim/system.cc
src/sim/system.hh
src/unittest/SConscript
util/regress