allow MSR reset to default to a value set by issuer_verilog.py
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Dec 2021 17:05:53 +0000 (17:05 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Dec 2021 17:05:53 +0000 (17:05 +0000)
commit292cc4f8c58404dd842f39ddd3cf18c9d56cf95d
tree5c74a23b686f9b70d104e7ebceeb7c25cd79199e
parente143a6750feb38427cfd53aa011ec07343f53a0c
allow MSR reset to default to a value set by issuer_verilog.py
src/soc/regfile/regfiles.py
src/soc/simple/core.py