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(parent: 8a8e2c0) | patch
use SPRreduced to match PowerDecoder2
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 1 May 2021 13:15:10 +0000 (14:15 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 1 May 2021 13:15:10 +0000 (14:15 +0100)
commit3e26c8a60b63db8bc0e1b324c5c1cc95beb37d91
tree2c37a2cbfb319c88053d22264d72e31d374dfa7atree
parent8a8e2c01cd4e9ef560b8a9cb29f59ffee5ff0420commit | diff
use SPRreduced to match PowerDecoder2
extend mmu_sprs to include redirection of PRTBL DSISR DAR and PIDR to MMU
src/soc/simple/test/test_core.py diff | blob | history