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(parent: 5fb6590) | patch
add pause_dec_tb signal (not very sophisticated) to Core
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 17 Jan 2022 11:59:56 +0000 (11:59 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 17 Jan 2022 11:59:56 +0000 (11:59 +0000)
commit44a11285f257bc65131805961ff947b51e25397a
tree8fd12b78554315b306ed13f974fe617afa3bfa18tree
parent5fb659041e7ef39cc469943422e154cb4223aa1acommit | diff
add pause_dec_tb signal (not very sophisticated) to Core
TODO, detect MTSPR and DEC/TB SPR being written to, but for now just
detect an entire SPR pipeline
src/soc/simple/core.py diff | blob | history