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(parent: 837d9fb) | patch
add div FSM as default for test_issuer in verilog and ilang gen
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 5 Aug 2020 09:29:44 +0000 (10:29 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 5 Aug 2020 09:29:44 +0000 (10:29 +0100)
commit4cb01cbff73a8e5cf74282f260be6a9a1f666b00
tree4418a5797a9cf1cb0a0e6d19d9ceb2563df614f7tree
parent837d9fbdd54265a63a07e475b6d85313cadf2927commit | diff
add div FSM as default for test_issuer in verilog and ilang gen
src/soc/fu/compunits/compunits.py diff | blob | history
src/soc/simple/issuer.py diff | blob | history
src/soc/simple/issuer_verilog.py diff | blob | history