projects / soc.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: f737a8a) | patch
add asserts to check data output is correct
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 20 Jun 2020 12:16:00 +0000 (13:16 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 20 Jun 2020 12:16:00 +0000 (13:16 +0100)
commit52215e08906096690085424fb4302c694f0793df
tree4227bc3264e214d501ccf9d6903cd44842ab7b0ftree
parentf737a8a27c245cec9fe959a6d4b76fb786626505commit | diff
add asserts to check data output is correct
src/soc/bus/test/test_sram_wishbone.py diff | blob | history