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(parent: dcc2a29) | patch
damn. assigning to temporary signals may turn out to be crucial. it could
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 20 May 2020 17:41:05 +0000 (18:41 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 20 May 2020 17:41:05 +0000 (18:41 +0100)
commit60f06a9eb815419f0477a5501c627824da07e078
tree6957cb55faad74692a4d2a742f016e18cc559a96tree
parentdcc2a29f28215104a85371e71787efb854a6aabacommit | diff
damn.  assigning to temporary signals may turn out to be crucial.  it could
just be something that affects Arrays: generating the ilang for CR pipeline
went mental.  100% CPU for several minutes.  bad sign
src/soc/fu/cr/main_stage.py diff | blob | history