reduce mem width due to yosys bugs. sigh
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Dec 2020 16:18:19 +0000 (16:18 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 3 Dec 2020 16:18:19 +0000 (16:18 +0000)
commit62a99f3cb3bf6658609ef0ebc8afeed9847fbf8b
tree2a49977ed5fc071cfdfd45965577625415397e6d
parentdf409461a7320964e5459bf9ea130ee10d338887
reduce mem width due to yosys bugs.  sigh
experiments9/non_generated/full_core_ls180.il