reduce mem width due to yosys bugs. sigh

diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il
index 435fe721ff955049bee613bdff84eacb0c7623ce..fe264d330649d516b6a3d544329a9c08a226ba0c 100644 (file)
--- a/experiments9/non_generated/full_core_ls180.il
+++ b/experiments9/non_generated/full_core_ls180.il
@@ -220714,193 +220714,193 @@ attribute \src "ls180.v:4.1-10811.10"
 attribute \cells_not_processed 1
 module \ls180
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0$memwr$\mem$ls180.v:10209$1_ADDR[8:0]$2823
+  wire width 6 $0$memwr$\mem$ls180.v:10209$1_ADDR[5:0]$2823
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10209$1_DATA[63:0]$2824
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10209$1_EN[63:0]$2825
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0$memwr$\mem$ls180.v:10211$2_ADDR[8:0]$2826
+  wire width 6 $0$memwr$\mem$ls180.v:10211$2_ADDR[5:0]$2826
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10211$2_DATA[63:0]$2827
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10211$2_EN[63:0]$2828
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0$memwr$\mem$ls180.v:10213$3_ADDR[8:0]$2829
+  wire width 6 $0$memwr$\mem$ls180.v:10213$3_ADDR[5:0]$2829
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10213$3_DATA[63:0]$2830
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10213$3_EN[63:0]$2831
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0$memwr$\mem$ls180.v:10215$4_ADDR[8:0]$2832
+  wire width 6 $0$memwr$\mem$ls180.v:10215$4_ADDR[5:0]$2832
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10215$4_DATA[63:0]$2833
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10215$4_EN[63:0]$2834
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0$memwr$\mem$ls180.v:10217$5_ADDR[8:0]$2835
+  wire width 6 $0$memwr$\mem$ls180.v:10217$5_ADDR[5:0]$2835
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10217$5_DATA[63:0]$2836
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10217$5_EN[63:0]$2837
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0$memwr$\mem$ls180.v:10219$6_ADDR[8:0]$2838
+  wire width 6 $0$memwr$\mem$ls180.v:10219$6_ADDR[5:0]$2838
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10219$6_DATA[63:0]$2839
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10219$6_EN[63:0]$2840
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0$memwr$\mem$ls180.v:10221$7_ADDR[8:0]$2841
+  wire width 6 $0$memwr$\mem$ls180.v:10221$7_ADDR[5:0]$2841
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10221$7_DATA[63:0]$2842
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10221$7_EN[63:0]$2843
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0$memwr$\mem$ls180.v:10223$8_ADDR[8:0]$2844
+  wire width 6 $0$memwr$\mem$ls180.v:10223$8_ADDR[5:0]$2844
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10223$8_DATA[63:0]$2845
   attribute \src "ls180.v:10207.1-10225.4"
   wire width 64 $0$memwr$\mem$ls180.v:10223$8_EN[63:0]$2846
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0$memwr$\mem_1$ls180.v:10237$9_ADDR[8:0]$2849
+  wire width 6 $0$memwr$\mem_1$ls180.v:10237$9_ADDR[5:0]$2849
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10237$9_DATA[63:0]$2850
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10237$9_EN[63:0]$2851
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0$memwr$\mem_1$ls180.v:10239$10_ADDR[8:0]$2852
+  wire width 6 $0$memwr$\mem_1$ls180.v:10239$10_ADDR[5:0]$2852
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10239$10_DATA[63:0]$2853
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10239$10_EN[63:0]$2854
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0$memwr$\mem_1$ls180.v:10241$11_ADDR[8:0]$2855
+  wire width 6 $0$memwr$\mem_1$ls180.v:10241$11_ADDR[5:0]$2855
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10241$11_DATA[63:0]$2856
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10241$11_EN[63:0]$2857
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0$memwr$\mem_1$ls180.v:10243$12_ADDR[8:0]$2858
+  wire width 6 $0$memwr$\mem_1$ls180.v:10243$12_ADDR[5:0]$2858
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10243$12_DATA[63:0]$2859
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10243$12_EN[63:0]$2860
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0$memwr$\mem_1$ls180.v:10245$13_ADDR[8:0]$2861
+  wire width 6 $0$memwr$\mem_1$ls180.v:10245$13_ADDR[5:0]$2861
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10245$13_DATA[63:0]$2862
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10245$13_EN[63:0]$2863
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0$memwr$\mem_1$ls180.v:10247$14_ADDR[8:0]$2864
+  wire width 6 $0$memwr$\mem_1$ls180.v:10247$14_ADDR[5:0]$2864
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10247$14_DATA[63:0]$2865
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10247$14_EN[63:0]$2866
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0$memwr$\mem_1$ls180.v:10249$15_ADDR[8:0]$2867
+  wire width 6 $0$memwr$\mem_1$ls180.v:10249$15_ADDR[5:0]$2867
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10249$15_DATA[63:0]$2868
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10249$15_EN[63:0]$2869
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0$memwr$\mem_1$ls180.v:10251$16_ADDR[8:0]$2870
+  wire width 6 $0$memwr$\mem_1$ls180.v:10251$16_ADDR[5:0]$2870
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10251$16_DATA[63:0]$2871
   attribute \src "ls180.v:10235.1-10253.4"
   wire width 64 $0$memwr$\mem_1$ls180.v:10251$16_EN[63:0]$2872
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0$memwr$\mem_2$ls180.v:10265$17_ADDR[8:0]$2875
+  wire width 6 $0$memwr$\mem_2$ls180.v:10265$17_ADDR[5:0]$2875
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10265$17_DATA[63:0]$2876
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10265$17_EN[63:0]$2877
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0$memwr$\mem_2$ls180.v:10267$18_ADDR[8:0]$2878
+  wire width 6 $0$memwr$\mem_2$ls180.v:10267$18_ADDR[5:0]$2878
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10267$18_DATA[63:0]$2879
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10267$18_EN[63:0]$2880
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0$memwr$\mem_2$ls180.v:10269$19_ADDR[8:0]$2881
+  wire width 6 $0$memwr$\mem_2$ls180.v:10269$19_ADDR[5:0]$2881
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10269$19_DATA[63:0]$2882
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10269$19_EN[63:0]$2883
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0$memwr$\mem_2$ls180.v:10271$20_ADDR[8:0]$2884
+  wire width 6 $0$memwr$\mem_2$ls180.v:10271$20_ADDR[5:0]$2884
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10271$20_DATA[63:0]$2885
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10271$20_EN[63:0]$2886
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0$memwr$\mem_2$ls180.v:10273$21_ADDR[8:0]$2887
+  wire width 6 $0$memwr$\mem_2$ls180.v:10273$21_ADDR[5:0]$2887
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10273$21_DATA[63:0]$2888
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10273$21_EN[63:0]$2889
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0$memwr$\mem_2$ls180.v:10275$22_ADDR[8:0]$2890
+  wire width 6 $0$memwr$\mem_2$ls180.v:10275$22_ADDR[5:0]$2890
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10275$22_DATA[63:0]$2891
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10275$22_EN[63:0]$2892
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0$memwr$\mem_2$ls180.v:10277$23_ADDR[8:0]$2893
+  wire width 6 $0$memwr$\mem_2$ls180.v:10277$23_ADDR[5:0]$2893
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10277$23_DATA[63:0]$2894
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10277$23_EN[63:0]$2895
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0$memwr$\mem_2$ls180.v:10279$24_ADDR[8:0]$2896
+  wire width 6 $0$memwr$\mem_2$ls180.v:10279$24_ADDR[5:0]$2896
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10279$24_DATA[63:0]$2897
   attribute \src "ls180.v:10263.1-10281.4"
   wire width 64 $0$memwr$\mem_2$ls180.v:10279$24_EN[63:0]$2898
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0$memwr$\mem_3$ls180.v:10293$25_ADDR[8:0]$2901
+  wire width 6 $0$memwr$\mem_3$ls180.v:10293$25_ADDR[5:0]$2901
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10293$25_DATA[63:0]$2902
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10293$25_EN[63:0]$2903
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0$memwr$\mem_3$ls180.v:10295$26_ADDR[8:0]$2904
+  wire width 6 $0$memwr$\mem_3$ls180.v:10295$26_ADDR[5:0]$2904
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10295$26_DATA[63:0]$2905
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10295$26_EN[63:0]$2906
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0$memwr$\mem_3$ls180.v:10297$27_ADDR[8:0]$2907
+  wire width 6 $0$memwr$\mem_3$ls180.v:10297$27_ADDR[5:0]$2907
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10297$27_DATA[63:0]$2908
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10297$27_EN[63:0]$2909
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0$memwr$\mem_3$ls180.v:10299$28_ADDR[8:0]$2910
+  wire width 6 $0$memwr$\mem_3$ls180.v:10299$28_ADDR[5:0]$2910
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10299$28_DATA[63:0]$2911
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10299$28_EN[63:0]$2912
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0$memwr$\mem_3$ls180.v:10301$29_ADDR[8:0]$2913
+  wire width 6 $0$memwr$\mem_3$ls180.v:10301$29_ADDR[5:0]$2913
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10301$29_DATA[63:0]$2914
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10301$29_EN[63:0]$2915
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0$memwr$\mem_3$ls180.v:10303$30_ADDR[8:0]$2916
+  wire width 6 $0$memwr$\mem_3$ls180.v:10303$30_ADDR[5:0]$2916
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10303$30_DATA[63:0]$2917
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10303$30_EN[63:0]$2918
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0$memwr$\mem_3$ls180.v:10305$31_ADDR[8:0]$2919
+  wire width 6 $0$memwr$\mem_3$ls180.v:10305$31_ADDR[5:0]$2919
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10305$31_DATA[63:0]$2920
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10305$31_EN[63:0]$2921
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0$memwr$\mem_3$ls180.v:10307$32_ADDR[8:0]$2922
+  wire width 6 $0$memwr$\mem_3$ls180.v:10307$32_ADDR[5:0]$2922
   attribute \src "ls180.v:10291.1-10309.4"
   wire width 64 $0$memwr$\mem_3$ls180.v:10307$32_DATA[63:0]$2923
   attribute \src "ls180.v:10291.1-10309.4"
@@ -222862,13 +222862,13 @@ module \ls180
   attribute \src "ls180.v:7564.1-10203.4"
   wire $0\main_wdata_consumed[0:0]
   attribute \src "ls180.v:10207.1-10225.4"
-  wire width 9 $0\memadr[8:0]
+  wire width 6 $0\memadr[5:0]
   attribute \src "ls180.v:10235.1-10253.4"
-  wire width 9 $0\memadr_1[8:0]
+  wire width 6 $0\memadr_1[5:0]
   attribute \src "ls180.v:10263.1-10281.4"
-  wire width 9 $0\memadr_2[8:0]
+  wire width 6 $0\memadr_2[5:0]
   attribute \src "ls180.v:10291.1-10309.4"
-  wire width 9 $0\memadr_3[8:0]
+  wire width 6 $0\memadr_3[5:0]
   attribute \src "ls180.v:10319.1-10323.4"
   wire width 25 $0\memdat[24:0]
   attribute \src "ls180.v:10333.1-10337.4"
@@ -227371,9 +227371,9 @@ module \ls180
   wire $eq$ls180.v:5818$1165_Y
   attribute \src "ls180.v:5819.27-5819.59"
   wire $eq$ls180.v:5819$1166_Y
-  attribute \src "ls180.v:5820.27-5820.59"
+  attribute \src "ls180.v:5820.27-5820.60"
   wire $eq$ls180.v:5820$1167_Y
-  attribute \src "ls180.v:5821.27-5821.59"
+  attribute \src "ls180.v:5821.27-5821.60"
   wire $eq$ls180.v:5821$1168_Y
   attribute \src "ls180.v:5822.27-5822.68"
   wire $eq$ls180.v:5822$1169_Y
@@ -228200,193 +228200,193 @@ module \ls180
   attribute \src "ls180.v:10433.45-10433.54"
   wire width 10 $memrd$\storage_7$ls180.v:10433$2981_DATA
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem$ls180.v:10209$1_ADDR
+  wire width 6 $memwr$\mem$ls180.v:10209$1_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10209$1_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10209$1_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem$ls180.v:10211$2_ADDR
+  wire width 6 $memwr$\mem$ls180.v:10211$2_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10211$2_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10211$2_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem$ls180.v:10213$3_ADDR
+  wire width 6 $memwr$\mem$ls180.v:10213$3_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10213$3_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10213$3_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem$ls180.v:10215$4_ADDR
+  wire width 6 $memwr$\mem$ls180.v:10215$4_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10215$4_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10215$4_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem$ls180.v:10217$5_ADDR
+  wire width 6 $memwr$\mem$ls180.v:10217$5_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10217$5_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10217$5_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem$ls180.v:10219$6_ADDR
+  wire width 6 $memwr$\mem$ls180.v:10219$6_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10219$6_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10219$6_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem$ls180.v:10221$7_ADDR
+  wire width 6 $memwr$\mem$ls180.v:10221$7_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10221$7_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10221$7_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem$ls180.v:10223$8_ADDR
+  wire width 6 $memwr$\mem$ls180.v:10223$8_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10223$8_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem$ls180.v:10223$8_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_1$ls180.v:10237$9_ADDR
+  wire width 6 $memwr$\mem_1$ls180.v:10237$9_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10237$9_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10237$9_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_1$ls180.v:10239$10_ADDR
+  wire width 6 $memwr$\mem_1$ls180.v:10239$10_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10239$10_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10239$10_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_1$ls180.v:10241$11_ADDR
+  wire width 6 $memwr$\mem_1$ls180.v:10241$11_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10241$11_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10241$11_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_1$ls180.v:10243$12_ADDR
+  wire width 6 $memwr$\mem_1$ls180.v:10243$12_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10243$12_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10243$12_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_1$ls180.v:10245$13_ADDR
+  wire width 6 $memwr$\mem_1$ls180.v:10245$13_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10245$13_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10245$13_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_1$ls180.v:10247$14_ADDR
+  wire width 6 $memwr$\mem_1$ls180.v:10247$14_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10247$14_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10247$14_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_1$ls180.v:10249$15_ADDR
+  wire width 6 $memwr$\mem_1$ls180.v:10249$15_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10249$15_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10249$15_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_1$ls180.v:10251$16_ADDR
+  wire width 6 $memwr$\mem_1$ls180.v:10251$16_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10251$16_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_1$ls180.v:10251$16_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_2$ls180.v:10265$17_ADDR
+  wire width 6 $memwr$\mem_2$ls180.v:10265$17_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10265$17_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10265$17_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_2$ls180.v:10267$18_ADDR
+  wire width 6 $memwr$\mem_2$ls180.v:10267$18_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10267$18_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10267$18_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_2$ls180.v:10269$19_ADDR
+  wire width 6 $memwr$\mem_2$ls180.v:10269$19_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10269$19_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10269$19_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_2$ls180.v:10271$20_ADDR
+  wire width 6 $memwr$\mem_2$ls180.v:10271$20_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10271$20_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10271$20_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_2$ls180.v:10273$21_ADDR
+  wire width 6 $memwr$\mem_2$ls180.v:10273$21_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10273$21_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10273$21_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_2$ls180.v:10275$22_ADDR
+  wire width 6 $memwr$\mem_2$ls180.v:10275$22_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10275$22_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10275$22_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_2$ls180.v:10277$23_ADDR
+  wire width 6 $memwr$\mem_2$ls180.v:10277$23_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10277$23_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10277$23_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_2$ls180.v:10279$24_ADDR
+  wire width 6 $memwr$\mem_2$ls180.v:10279$24_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10279$24_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_2$ls180.v:10279$24_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_3$ls180.v:10293$25_ADDR
+  wire width 6 $memwr$\mem_3$ls180.v:10293$25_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10293$25_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10293$25_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_3$ls180.v:10295$26_ADDR
+  wire width 6 $memwr$\mem_3$ls180.v:10295$26_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10295$26_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10295$26_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_3$ls180.v:10297$27_ADDR
+  wire width 6 $memwr$\mem_3$ls180.v:10297$27_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10297$27_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10297$27_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_3$ls180.v:10299$28_ADDR
+  wire width 6 $memwr$\mem_3$ls180.v:10299$28_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10299$28_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10299$28_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_3$ls180.v:10301$29_ADDR
+  wire width 6 $memwr$\mem_3$ls180.v:10301$29_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10301$29_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10301$29_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_3$ls180.v:10303$30_ADDR
+  wire width 6 $memwr$\mem_3$ls180.v:10303$30_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10303$30_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10303$30_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_3$ls180.v:10305$31_ADDR
+  wire width 6 $memwr$\mem_3$ls180.v:10305$31_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10305$31_DATA
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10305$31_EN
   attribute \src "ls180.v:0.0-0.0"
-  wire width 9 $memwr$\mem_3$ls180.v:10307$32_ADDR
+  wire width 6 $memwr$\mem_3$ls180.v:10307$32_ADDR
   attribute \src "ls180.v:0.0-0.0"
   wire width 64 $memwr$\mem_3$ls180.v:10307$32_DATA
   attribute \src "ls180.v:0.0-0.0"
@@ -231965,24 +231965,24 @@ module \ls180
   wire \builder_sync_rhs_array_muxed6
   attribute \src "ls180.v:1946.6-1946.18"
   wire \builder_wait
-  attribute \src "ls180.v:33.19-33.23"
-  wire width 3 input 29 \eint
-  attribute \src "ls180.v:150.12-150.18"
+  attribute \src "ls180.v:5.19-5.23"
+  wire width 3 input 1 \eint
+  attribute \src "ls180.v:127.12-127.18"
   wire width 3 \eint_1
-  attribute \src "ls180.v:11.20-11.26"
-  wire width 16 input 7 \gpio_i
-  attribute \src "ls180.v:12.21-12.27"
-  wire width 16 output 8 \gpio_o
-  attribute \src "ls180.v:13.21-13.28"
-  wire width 16 output 9 \gpio_oe
-  attribute \src "ls180.v:35.14-35.21"
-  wire output 31 \i2c_scl
-  attribute \src "ls180.v:36.13-36.22"
-  wire input 32 \i2c_sda_i
-  attribute \src "ls180.v:37.14-37.23"
-  wire output 33 \i2c_sda_o
-  attribute \src "ls180.v:38.14-38.24"
-  wire output 34 \i2c_sda_oe
+  attribute \src "ls180.v:27.20-27.26"
+  wire width 16 input 23 \gpio_i
+  attribute \src "ls180.v:28.21-28.27"
+  wire width 16 output 24 \gpio_o
+  attribute \src "ls180.v:29.21-29.28"
+  wire width 16 output 25 \gpio_oe
+  attribute \src "ls180.v:6.14-6.21"
+  wire output 2 \i2c_scl
+  attribute \src "ls180.v:7.13-7.22"
+  wire input 3 \i2c_sda_i
+  attribute \src "ls180.v:8.14-8.23"
+  wire output 4 \i2c_sda_o
+  attribute \src "ls180.v:9.14-9.24"
+  wire output 5 \i2c_sda_oe
   attribute \src "ls180.v:49.13-49.21"
   wire input 45 \jtag_tck
   attribute \src "ls180.v:50.13-50.21"
@@ -232260,7 +232260,7 @@ module \ls180
   attribute \src "ls180.v:239.6-239.32"
   wire \main_interface2_ram_bus_we
   attribute \src "ls180.v:171.12-171.32"
-  wire width 9 \main_libresocsim_adr
+  wire width 6 \main_libresocsim_adr
   attribute \src "ls180.v:62.6-62.32"
   wire \main_libresocsim_bus_error
   attribute \src "ls180.v:63.12-63.39"
@@ -232307,65 +232307,65 @@ module \ls180
   wire width 64 \main_libresocsim_libresoc2
   attribute \src "ls180.v:125.12-125.45"
   wire width 2 \main_libresocsim_libresoc_clk_sel
-  attribute \src "ls180.v:131.13-131.67"
+  attribute \src "ls180.v:144.13-144.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
-  attribute \src "ls180.v:132.13-132.67"
+  attribute \src "ls180.v:145.13-145.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
-  attribute \src "ls180.v:133.13-133.68"
+  attribute \src "ls180.v:146.13-146.68"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
-  attribute \src "ls180.v:152.6-152.61"
+  attribute \src "ls180.v:128.6-128.61"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
-  attribute \src "ls180.v:153.6-153.63"
+  attribute \src "ls180.v:129.6-129.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
-  attribute \src "ls180.v:154.6-154.63"
+  attribute \src "ls180.v:130.6-130.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
-  attribute \src "ls180.v:155.6-155.64"
+  attribute \src "ls180.v:131.6-131.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
-  attribute \src "ls180.v:134.6-134.64"
+  attribute \src "ls180.v:140.6-140.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
-  attribute \src "ls180.v:135.6-135.66"
+  attribute \src "ls180.v:141.6-141.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
-  attribute \src "ls180.v:136.6-136.66"
+  attribute \src "ls180.v:142.6-142.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
-  attribute \src "ls180.v:137.6-137.67"
+  attribute \src "ls180.v:143.6-143.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
-  attribute \src "ls180.v:138.13-138.68"
+  attribute \src "ls180.v:147.13-147.68"
   wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
-  attribute \src "ls180.v:147.12-147.68"
+  attribute \src "ls180.v:156.12-156.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
-  attribute \src "ls180.v:144.6-144.65"
+  attribute \src "ls180.v:153.6-153.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
-  attribute \src "ls180.v:146.6-146.63"
+  attribute \src "ls180.v:155.6-155.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
-  attribute \src "ls180.v:145.6-145.64"
+  attribute \src "ls180.v:154.6-154.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
-  attribute \src "ls180.v:148.12-148.68"
+  attribute \src "ls180.v:157.12-157.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
-  attribute \src "ls180.v:139.13-139.71"
+  attribute \src "ls180.v:148.13-148.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
-  attribute \src "ls180.v:140.13-140.71"
+  attribute \src "ls180.v:149.13-149.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
-  attribute \src "ls180.v:141.6-141.65"
+  attribute \src "ls180.v:150.6-150.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
-  attribute \src "ls180.v:143.6-143.65"
+  attribute \src "ls180.v:152.6-152.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
-  attribute \src "ls180.v:142.6-142.64"
+  attribute \src "ls180.v:151.6-151.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
-  attribute \src "ls180.v:156.6-156.67"
+  attribute \src "ls180.v:136.6-136.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
-  attribute \src "ls180.v:158.6-158.68"
+  attribute \src "ls180.v:138.6-138.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
-  attribute \src "ls180.v:159.6-159.68"
+  attribute \src "ls180.v:139.6-139.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
-  attribute \src "ls180.v:157.6-157.68"
+  attribute \src "ls180.v:137.6-137.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
-  attribute \src "ls180.v:127.6-127.67"
+  attribute \src "ls180.v:132.6-132.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
-  attribute \src "ls180.v:129.6-129.68"
+  attribute \src "ls180.v:134.6-134.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
-  attribute \src "ls180.v:130.6-130.68"
+  attribute \src "ls180.v:135.6-135.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
-  attribute \src "ls180.v:128.6-128.68"
+  attribute \src "ls180.v:133.6-133.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
   attribute \src "ls180.v:72.6-72.40"
   wire \main_libresocsim_libresoc_dbus_ack
@@ -235240,7 +235240,7 @@ module \ls180
   attribute \src "ls180.v:1083.6-1083.30"
   wire \main_spisdcard_status_we
   attribute \src "ls180.v:213.12-213.26"
-  wire width 9 \main_sram0_adr
+  wire width 6 \main_sram0_adr
   attribute \src "ls180.v:214.13-214.29"
   wire width 64 \main_sram0_dat_r
   attribute \src "ls180.v:216.13-216.29"
@@ -235248,7 +235248,7 @@ module \ls180
   attribute \src "ls180.v:215.11-215.24"
   wire width 8 \main_sram0_we
   attribute \src "ls180.v:228.12-228.26"
-  wire width 9 \main_sram1_adr
+  wire width 6 \main_sram1_adr
   attribute \src "ls180.v:229.13-229.29"
   wire width 64 \main_sram1_dat_r
   attribute \src "ls180.v:231.13-231.29"
@@ -235256,7 +235256,7 @@ module \ls180
   attribute \src "ls180.v:230.11-230.24"
   wire width 8 \main_sram1_we
   attribute \src "ls180.v:243.12-243.26"
-  wire width 9 \main_sram2_adr
+  wire width 6 \main_sram2_adr
   attribute \src "ls180.v:244.13-244.29"
   wire width 64 \main_sram2_dat_r
   attribute \src "ls180.v:246.13-246.29"
@@ -235566,13 +235566,13 @@ module \ls180
   attribute \src "ls180.v:877.5-877.24"
   wire \main_wdata_consumed
   attribute \src "ls180.v:10206.11-10206.17"
-  wire width 9 \memadr
+  wire width 6 \memadr
   attribute \src "ls180.v:10234.11-10234.19"
-  wire width 9 \memadr_1
+  wire width 6 \memadr_1
   attribute \src "ls180.v:10262.11-10262.19"
-  wire width 9 \memadr_2
+  wire width 6 \memadr_2
   attribute \src "ls180.v:10290.11-10290.19"
-  wire width 9 \memadr_3
+  wire width 6 \memadr_3
   attribute \src "ls180.v:10318.12-10318.18"
   wire width 25 \memdat
   attribute \src "ls180.v:10332.12-10332.20"
@@ -235597,50 +235597,50 @@ module \ls180
   wire width 24 input 48 \nc
   attribute \src "ls180.v:279.6-279.13"
   wire \por_clk
-  attribute \src "ls180.v:34.19-34.22"
-  wire width 2 output 30 \pwm
-  attribute \src "ls180.v:151.12-151.17"
+  attribute \src "ls180.v:42.19-42.22"
+  wire width 2 output 38 \pwm
+  attribute \src "ls180.v:159.12-159.17"
   wire width 2 \pwm_1
-  attribute \src "ls180.v:14.13-14.23"
-  wire output 10 \sdcard_clk
-  attribute \src "ls180.v:15.13-15.25"
-  wire input 11 \sdcard_cmd_i
-  attribute \src "ls180.v:16.13-16.25"
-  wire output 12 \sdcard_cmd_o
-  attribute \src "ls180.v:17.13-17.26"
-  wire output 13 \sdcard_cmd_oe
-  attribute \src "ls180.v:18.19-18.32"
-  wire width 4 input 14 \sdcard_data_i
-  attribute \src "ls180.v:19.19-19.32"
-  wire width 4 output 15 \sdcard_data_o
-  attribute \src "ls180.v:20.13-20.27"
-  wire output 16 \sdcard_data_oe
-  attribute \src "ls180.v:21.20-21.27"
-  wire width 13 output 17 \sdram_a
-  attribute \src "ls180.v:30.19-30.27"
-  wire width 2 output 26 \sdram_ba
-  attribute \src "ls180.v:27.13-27.24"
-  wire output 23 \sdram_cas_n
-  attribute \src "ls180.v:29.13-29.22"
-  wire output 25 \sdram_cke
-  attribute \src "ls180.v:32.13-32.24"
-  wire output 28 \sdram_clock
-  attribute \src "ls180.v:149.6-149.19"
+  attribute \src "ls180.v:20.13-20.23"
+  wire output 16 \sdcard_clk
+  attribute \src "ls180.v:21.13-21.25"
+  wire input 17 \sdcard_cmd_i
+  attribute \src "ls180.v:22.13-22.25"
+  wire output 18 \sdcard_cmd_o
+  attribute \src "ls180.v:23.13-23.26"
+  wire output 19 \sdcard_cmd_oe
+  attribute \src "ls180.v:24.19-24.32"
+  wire width 4 input 20 \sdcard_data_i
+  attribute \src "ls180.v:25.19-25.32"
+  wire width 4 output 21 \sdcard_data_o
+  attribute \src "ls180.v:26.13-26.27"
+  wire output 22 \sdcard_data_oe
+  attribute \src "ls180.v:30.20-30.27"
+  wire width 13 output 26 \sdram_a
+  attribute \src "ls180.v:39.19-39.27"
+  wire width 2 output 35 \sdram_ba
+  attribute \src "ls180.v:36.13-36.24"
+  wire output 32 \sdram_cas_n
+  attribute \src "ls180.v:38.13-38.22"
+  wire output 34 \sdram_cke
+  attribute \src "ls180.v:41.13-41.24"
+  wire output 37 \sdram_clock
+  attribute \src "ls180.v:158.6-158.19"
   wire \sdram_clock_1
-  attribute \src "ls180.v:28.13-28.23"
-  wire output 24 \sdram_cs_n
-  attribute \src "ls180.v:31.19-31.27"
-  wire width 2 output 27 \sdram_dm
-  attribute \src "ls180.v:22.20-22.30"
-  wire width 16 input 18 \sdram_dq_i
-  attribute \src "ls180.v:23.20-23.30"
-  wire width 16 output 19 \sdram_dq_o
-  attribute \src "ls180.v:24.13-24.24"
-  wire output 20 \sdram_dq_oe
-  attribute \src "ls180.v:26.13-26.24"
-  wire output 22 \sdram_ras_n
-  attribute \src "ls180.v:25.13-25.23"
-  wire output 21 \sdram_we_n
+  attribute \src "ls180.v:37.13-37.23"
+  wire output 33 \sdram_cs_n
+  attribute \src "ls180.v:40.19-40.27"
+  wire width 2 output 36 \sdram_dm
+  attribute \src "ls180.v:31.20-31.30"
+  wire width 16 input 27 \sdram_dq_i
+  attribute \src "ls180.v:32.20-32.30"
+  wire width 16 output 28 \sdram_dq_o
+  attribute \src "ls180.v:33.13-33.24"
+  wire output 29 \sdram_dq_oe
+  attribute \src "ls180.v:35.13-35.24"
+  wire output 31 \sdram_ras_n
+  attribute \src "ls180.v:34.13-34.23"
+  wire output 30 \sdram_we_n
   attribute \src "ls180.v:2695.6-2695.15"
   wire \sdrio_clk
   attribute \src "ls180.v:2696.6-2696.17"
@@ -235779,22 +235779,22 @@ module \ls180
   wire \sdrio_clk_8
   attribute \src "ls180.v:2704.6-2704.17"
   wire \sdrio_clk_9
-  attribute \src "ls180.v:39.13-39.26"
-  wire output 35 \spimaster_clk
-  attribute \src "ls180.v:41.13-41.27"
-  wire output 37 \spimaster_cs_n
-  attribute \src "ls180.v:42.13-42.27"
-  wire input 38 \spimaster_miso
-  attribute \src "ls180.v:40.13-40.27"
-  wire output 36 \spimaster_mosi
-  attribute \src "ls180.v:5.13-5.26"
-  wire output 1 \spisdcard_clk
-  attribute \src "ls180.v:7.13-7.27"
-  wire output 3 \spisdcard_cs_n
-  attribute \src "ls180.v:8.13-8.27"
-  wire input 4 \spisdcard_miso
-  attribute \src "ls180.v:6.13-6.27"
-  wire output 2 \spisdcard_mosi
+  attribute \src "ls180.v:16.13-16.26"
+  wire output 12 \spimaster_clk
+  attribute \src "ls180.v:18.13-18.27"
+  wire output 14 \spimaster_cs_n
+  attribute \src "ls180.v:19.13-19.27"
+  wire input 15 \spimaster_miso
+  attribute \src "ls180.v:17.13-17.27"
+  wire output 13 \spimaster_mosi
+  attribute \src "ls180.v:12.13-12.26"
+  wire output 8 \spisdcard_clk
+  attribute \src "ls180.v:14.13-14.27"
+  wire output 10 \spisdcard_cs_n
+  attribute \src "ls180.v:15.13-15.27"
+  wire input 11 \spisdcard_miso
+  attribute \src "ls180.v:13.13-13.27"
+  wire output 9 \spisdcard_mosi
   attribute \src "ls180.v:43.13-43.20"
   wire input 39 \sys_clk
   attribute \src "ls180.v:277.6-277.15"
@@ -235809,18 +235809,18 @@ module \ls180
   wire input 40 \sys_rst
   attribute \src "ls180.v:278.6-278.15"
   wire \sys_rst_1
+  attribute \src "ls180.v:11.13-11.20"
+  wire input 7 \uart_rx
   attribute \src "ls180.v:10.13-10.20"
-  wire input 6 \uart_rx
-  attribute \src "ls180.v:9.13-9.20"
-  wire output 5 \uart_tx
+  wire output 6 \uart_tx
   attribute \src "ls180.v:10205.12-10205.15"
-  memory width 64 size 512 \mem
+  memory width 64 size 64 \mem
   attribute \src "ls180.v:10233.12-10233.17"
-  memory width 64 size 512 \mem_1
+  memory width 64 size 64 \mem_1
   attribute \src "ls180.v:10261.12-10261.17"
-  memory width 64 size 512 \mem_2
+  memory width 64 size 64 \mem_2
   attribute \src "ls180.v:10289.12-10289.17"
-  memory width 64 size 512 \mem_3
+  memory width 64 size 64 \mem_3
   attribute \src "ls180.v:10317.12-10317.19"
   memory width 25 size 8 \storage
   attribute \src "ls180.v:10331.12-10331.21"
@@ -251097,45 +251097,45 @@ module \ls180
   attribute \src "ls180.v:5818.27-5818.59"
   cell $eq $eq$ls180.v:5818$1165
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 21
+    parameter \A_WIDTH 24
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \builder_shared_adr [29:9]
+    connect \A \builder_shared_adr [29:6]
     connect \B 1'0
     connect \Y $eq$ls180.v:5818$1165_Y
   end
   attribute \src "ls180.v:5819.27-5819.59"
   cell $eq $eq$ls180.v:5819$1166
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 21
+    parameter \A_WIDTH 24
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \builder_shared_adr [29:9]
-    connect \B 1'1
+    connect \A \builder_shared_adr [29:6]
+    connect \B 4'1000
     connect \Y $eq$ls180.v:5819$1166_Y
   end
-  attribute \src "ls180.v:5820.27-5820.59"
+  attribute \src "ls180.v:5820.27-5820.60"
   cell $eq $eq$ls180.v:5820$1167
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 21
+    parameter \A_WIDTH 24
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
+    parameter \B_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \builder_shared_adr [29:9]
-    connect \B 2'10
+    connect \A \builder_shared_adr [29:6]
+    connect \B 5'10000
     connect \Y $eq$ls180.v:5820$1167_Y
   end
-  attribute \src "ls180.v:5821.27-5821.59"
+  attribute \src "ls180.v:5821.27-5821.60"
   cell $eq $eq$ls180.v:5821$1168
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 21
+    parameter \A_WIDTH 24
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
+    parameter \B_WIDTH 5
     parameter \Y_WIDTH 1
-    connect \A \builder_shared_adr [29:9]
-    connect \B 2'11
+    connect \A \builder_shared_adr [29:6]
+    connect \B 5'11000
     connect \Y $eq$ls180.v:5821$1168_Y
   end
   attribute \src "ls180.v:5822.27-5822.68"
@@ -255452,7 +255452,7 @@ module \ls180
   end
   attribute \src "ls180.v:10227.33-10227.36"
   cell $memrd $memrd$\mem$ls180.v:10227$2847
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255465,7 +255465,7 @@ module \ls180
   end
   attribute \src "ls180.v:10255.27-10255.32"
   cell $memrd $memrd$\mem_1$ls180.v:10255$2873
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255478,7 +255478,7 @@ module \ls180
   end
   attribute \src "ls180.v:10283.27-10283.32"
   cell $memrd $memrd$\mem_2$ls180.v:10283$2899
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -255491,7 +255491,7 @@ module \ls180
   end
   attribute \src "ls180.v:10311.27-10311.32"
   cell $memrd $memrd$\mem_3$ls180.v:10311$2925
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -255712,7 +255712,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem$ls180.v:0$2983
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255725,7 +255725,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem$ls180.v:0$2984
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255738,7 +255738,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem$ls180.v:0$2985
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255751,7 +255751,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem$ls180.v:0$2986
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255764,7 +255764,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem$ls180.v:0$2987
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255777,7 +255777,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem$ls180.v:0$2988
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255790,7 +255790,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem$ls180.v:0$2989
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255803,7 +255803,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem$ls180.v:0$2990
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem"
@@ -255816,7 +255816,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_1$ls180.v:0$2991
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255829,7 +255829,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_1$ls180.v:0$2992
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255842,7 +255842,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_1$ls180.v:0$2993
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255855,7 +255855,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_1$ls180.v:0$2994
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255868,7 +255868,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_1$ls180.v:0$2995
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255881,7 +255881,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_1$ls180.v:0$2996
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255894,7 +255894,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_1$ls180.v:0$2997
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255907,7 +255907,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_1$ls180.v:0$2998
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_1"
@@ -255920,7 +255920,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_2$ls180.v:0$2999
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -255933,7 +255933,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_2$ls180.v:0$3000
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -255946,7 +255946,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_2$ls180.v:0$3001
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -255959,7 +255959,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_2$ls180.v:0$3002
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -255972,7 +255972,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_2$ls180.v:0$3003
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -255985,7 +255985,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_2$ls180.v:0$3004
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -255998,7 +255998,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_2$ls180.v:0$3005
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -256011,7 +256011,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_2$ls180.v:0$3006
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_2"
@@ -256024,7 +256024,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_3$ls180.v:0$3007
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -256037,7 +256037,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_3$ls180.v:0$3008
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -256050,7 +256050,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_3$ls180.v:0$3009
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -256063,7 +256063,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_3$ls180.v:0$3010
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -256076,7 +256076,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_3$ls180.v:0$3011
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -256089,7 +256089,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_3$ls180.v:0$3012
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -256102,7 +256102,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_3$ls180.v:0$3013
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -256115,7 +256115,7 @@ module \ls180
   end
   attribute \src "ls180.v:0.0-0.0"
   cell $memwr $memwr$\mem_3$ls180.v:0$3014
-    parameter \ABITS 9
+    parameter \ABITS 6
     parameter \CLK_ENABLE 0
     parameter \CLK_POLARITY 0
     parameter \MEMID "\\mem_3"
@@ -265125,36 +265125,36 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\mem$ls180.v:10223$8_ADDR[8:0]$2844 9'xxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10223$8_ADDR[5:0]$2844 6'xxxxxx
     assign $0$memwr$\mem$ls180.v:10223$8_DATA[63:0]$2845 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem$ls180.v:10223$8_EN[63:0]$2846 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem$ls180.v:10221$7_ADDR[8:0]$2841 9'xxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10221$7_ADDR[5:0]$2841 6'xxxxxx
     assign $0$memwr$\mem$ls180.v:10221$7_DATA[63:0]$2842 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem$ls180.v:10221$7_EN[63:0]$2843 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem$ls180.v:10219$6_ADDR[8:0]$2838 9'xxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10219$6_ADDR[5:0]$2838 6'xxxxxx
     assign $0$memwr$\mem$ls180.v:10219$6_DATA[63:0]$2839 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem$ls180.v:10219$6_EN[63:0]$2840 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem$ls180.v:10217$5_ADDR[8:0]$2835 9'xxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10217$5_ADDR[5:0]$2835 6'xxxxxx
     assign $0$memwr$\mem$ls180.v:10217$5_DATA[63:0]$2836 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem$ls180.v:10217$5_EN[63:0]$2837 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem$ls180.v:10215$4_ADDR[8:0]$2832 9'xxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10215$4_ADDR[5:0]$2832 6'xxxxxx
     assign $0$memwr$\mem$ls180.v:10215$4_DATA[63:0]$2833 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem$ls180.v:10215$4_EN[63:0]$2834 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem$ls180.v:10213$3_ADDR[8:0]$2829 9'xxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10213$3_ADDR[5:0]$2829 6'xxxxxx
     assign $0$memwr$\mem$ls180.v:10213$3_DATA[63:0]$2830 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem$ls180.v:10213$3_EN[63:0]$2831 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem$ls180.v:10211$2_ADDR[8:0]$2826 9'xxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10211$2_ADDR[5:0]$2826 6'xxxxxx
     assign $0$memwr$\mem$ls180.v:10211$2_DATA[63:0]$2827 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem$ls180.v:10211$2_EN[63:0]$2828 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem$ls180.v:10209$1_ADDR[8:0]$2823 9'xxxxxxxxx
+    assign $0$memwr$\mem$ls180.v:10209$1_ADDR[5:0]$2823 6'xxxxxx
     assign $0$memwr$\mem$ls180.v:10209$1_DATA[63:0]$2824 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem$ls180.v:10209$1_EN[63:0]$2825 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0\memadr[8:0] \main_libresocsim_adr
+    assign $0\memadr[5:0] \main_libresocsim_adr
     attribute \src "ls180.v:10208.2-10209.65"
     switch \main_libresocsim_we [0]
       attribute \src "ls180.v:10208.6-10208.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10209$1_ADDR[8:0]$2823 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10209$1_ADDR[5:0]$2823 \main_libresocsim_adr
         assign $0$memwr$\mem$ls180.v:10209$1_DATA[63:0]$2824 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] }
         assign $0$memwr$\mem$ls180.v:10209$1_EN[63:0]$2825 64'0000000000000000000000000000000000000000000000000000000011111111
       case 
@@ -265163,7 +265163,7 @@ module \ls180
     switch \main_libresocsim_we [1]
       attribute \src "ls180.v:10210.6-10210.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10211$2_ADDR[8:0]$2826 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10211$2_ADDR[5:0]$2826 \main_libresocsim_adr
         assign $0$memwr$\mem$ls180.v:10211$2_DATA[63:0]$2827 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx }
         assign $0$memwr$\mem$ls180.v:10211$2_EN[63:0]$2828 64'0000000000000000000000000000000000000000000000001111111100000000
       case 
@@ -265172,7 +265172,7 @@ module \ls180
     switch \main_libresocsim_we [2]
       attribute \src "ls180.v:10212.6-10212.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10213$3_ADDR[8:0]$2829 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10213$3_ADDR[5:0]$2829 \main_libresocsim_adr
         assign $0$memwr$\mem$ls180.v:10213$3_DATA[63:0]$2830 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem$ls180.v:10213$3_EN[63:0]$2831 64'0000000000000000000000000000000000000000111111110000000000000000
       case 
@@ -265181,7 +265181,7 @@ module \ls180
     switch \main_libresocsim_we [3]
       attribute \src "ls180.v:10214.6-10214.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10215$4_ADDR[8:0]$2832 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10215$4_ADDR[5:0]$2832 \main_libresocsim_adr
         assign $0$memwr$\mem$ls180.v:10215$4_DATA[63:0]$2833 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem$ls180.v:10215$4_EN[63:0]$2834 64'0000000000000000000000000000000011111111000000000000000000000000
       case 
@@ -265190,7 +265190,7 @@ module \ls180
     switch \main_libresocsim_we [4]
       attribute \src "ls180.v:10216.6-10216.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10217$5_ADDR[8:0]$2835 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10217$5_ADDR[5:0]$2835 \main_libresocsim_adr
         assign $0$memwr$\mem$ls180.v:10217$5_DATA[63:0]$2836 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem$ls180.v:10217$5_EN[63:0]$2837 64'0000000000000000000000001111111100000000000000000000000000000000
       case 
@@ -265199,7 +265199,7 @@ module \ls180
     switch \main_libresocsim_we [5]
       attribute \src "ls180.v:10218.6-10218.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10219$6_ADDR[8:0]$2838 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10219$6_ADDR[5:0]$2838 \main_libresocsim_adr
         assign $0$memwr$\mem$ls180.v:10219$6_DATA[63:0]$2839 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem$ls180.v:10219$6_EN[63:0]$2840 64'0000000000000000111111110000000000000000000000000000000000000000
       case 
@@ -265208,7 +265208,7 @@ module \ls180
     switch \main_libresocsim_we [6]
       attribute \src "ls180.v:10220.6-10220.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10221$7_ADDR[8:0]$2841 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10221$7_ADDR[5:0]$2841 \main_libresocsim_adr
         assign $0$memwr$\mem$ls180.v:10221$7_DATA[63:0]$2842 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem$ls180.v:10221$7_EN[63:0]$2843 64'0000000011111111000000000000000000000000000000000000000000000000
       case 
@@ -265217,35 +265217,35 @@ module \ls180
     switch \main_libresocsim_we [7]
       attribute \src "ls180.v:10222.6-10222.28"
       case 1'1
-        assign $0$memwr$\mem$ls180.v:10223$8_ADDR[8:0]$2844 \main_libresocsim_adr
+        assign $0$memwr$\mem$ls180.v:10223$8_ADDR[5:0]$2844 \main_libresocsim_adr
         assign $0$memwr$\mem$ls180.v:10223$8_DATA[63:0]$2845 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem$ls180.v:10223$8_EN[63:0]$2846 64'1111111100000000000000000000000000000000000000000000000000000000
       case 
     end
     sync posedge \sys_clk_1
-      update \memadr $0\memadr[8:0]
-      update $memwr$\mem$ls180.v:10209$1_ADDR $0$memwr$\mem$ls180.v:10209$1_ADDR[8:0]$2823
+      update \memadr $0\memadr[5:0]
+      update $memwr$\mem$ls180.v:10209$1_ADDR $0$memwr$\mem$ls180.v:10209$1_ADDR[5:0]$2823
       update $memwr$\mem$ls180.v:10209$1_DATA $0$memwr$\mem$ls180.v:10209$1_DATA[63:0]$2824
       update $memwr$\mem$ls180.v:10209$1_EN $0$memwr$\mem$ls180.v:10209$1_EN[63:0]$2825
-      update $memwr$\mem$ls180.v:10211$2_ADDR $0$memwr$\mem$ls180.v:10211$2_ADDR[8:0]$2826
+      update $memwr$\mem$ls180.v:10211$2_ADDR $0$memwr$\mem$ls180.v:10211$2_ADDR[5:0]$2826
       update $memwr$\mem$ls180.v:10211$2_DATA $0$memwr$\mem$ls180.v:10211$2_DATA[63:0]$2827
       update $memwr$\mem$ls180.v:10211$2_EN $0$memwr$\mem$ls180.v:10211$2_EN[63:0]$2828
-      update $memwr$\mem$ls180.v:10213$3_ADDR $0$memwr$\mem$ls180.v:10213$3_ADDR[8:0]$2829
+      update $memwr$\mem$ls180.v:10213$3_ADDR $0$memwr$\mem$ls180.v:10213$3_ADDR[5:0]$2829
       update $memwr$\mem$ls180.v:10213$3_DATA $0$memwr$\mem$ls180.v:10213$3_DATA[63:0]$2830
       update $memwr$\mem$ls180.v:10213$3_EN $0$memwr$\mem$ls180.v:10213$3_EN[63:0]$2831
-      update $memwr$\mem$ls180.v:10215$4_ADDR $0$memwr$\mem$ls180.v:10215$4_ADDR[8:0]$2832
+      update $memwr$\mem$ls180.v:10215$4_ADDR $0$memwr$\mem$ls180.v:10215$4_ADDR[5:0]$2832
       update $memwr$\mem$ls180.v:10215$4_DATA $0$memwr$\mem$ls180.v:10215$4_DATA[63:0]$2833
       update $memwr$\mem$ls180.v:10215$4_EN $0$memwr$\mem$ls180.v:10215$4_EN[63:0]$2834
-      update $memwr$\mem$ls180.v:10217$5_ADDR $0$memwr$\mem$ls180.v:10217$5_ADDR[8:0]$2835
+      update $memwr$\mem$ls180.v:10217$5_ADDR $0$memwr$\mem$ls180.v:10217$5_ADDR[5:0]$2835
       update $memwr$\mem$ls180.v:10217$5_DATA $0$memwr$\mem$ls180.v:10217$5_DATA[63:0]$2836
       update $memwr$\mem$ls180.v:10217$5_EN $0$memwr$\mem$ls180.v:10217$5_EN[63:0]$2837
-      update $memwr$\mem$ls180.v:10219$6_ADDR $0$memwr$\mem$ls180.v:10219$6_ADDR[8:0]$2838
+      update $memwr$\mem$ls180.v:10219$6_ADDR $0$memwr$\mem$ls180.v:10219$6_ADDR[5:0]$2838
       update $memwr$\mem$ls180.v:10219$6_DATA $0$memwr$\mem$ls180.v:10219$6_DATA[63:0]$2839
       update $memwr$\mem$ls180.v:10219$6_EN $0$memwr$\mem$ls180.v:10219$6_EN[63:0]$2840
-      update $memwr$\mem$ls180.v:10221$7_ADDR $0$memwr$\mem$ls180.v:10221$7_ADDR[8:0]$2841
+      update $memwr$\mem$ls180.v:10221$7_ADDR $0$memwr$\mem$ls180.v:10221$7_ADDR[5:0]$2841
       update $memwr$\mem$ls180.v:10221$7_DATA $0$memwr$\mem$ls180.v:10221$7_DATA[63:0]$2842
       update $memwr$\mem$ls180.v:10221$7_EN $0$memwr$\mem$ls180.v:10221$7_EN[63:0]$2843
-      update $memwr$\mem$ls180.v:10223$8_ADDR $0$memwr$\mem$ls180.v:10223$8_ADDR[8:0]$2844
+      update $memwr$\mem$ls180.v:10223$8_ADDR $0$memwr$\mem$ls180.v:10223$8_ADDR[5:0]$2844
       update $memwr$\mem$ls180.v:10223$8_DATA $0$memwr$\mem$ls180.v:10223$8_DATA[63:0]$2845
       update $memwr$\mem$ls180.v:10223$8_EN $0$memwr$\mem$ls180.v:10223$8_EN[63:0]$2846
   end
@@ -265292,36 +265292,36 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\mem_1$ls180.v:10251$16_ADDR[8:0]$2870 9'xxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10251$16_ADDR[5:0]$2870 6'xxxxxx
     assign $0$memwr$\mem_1$ls180.v:10251$16_DATA[63:0]$2871 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_1$ls180.v:10251$16_EN[63:0]$2872 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_1$ls180.v:10249$15_ADDR[8:0]$2867 9'xxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10249$15_ADDR[5:0]$2867 6'xxxxxx
     assign $0$memwr$\mem_1$ls180.v:10249$15_DATA[63:0]$2868 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_1$ls180.v:10249$15_EN[63:0]$2869 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_1$ls180.v:10247$14_ADDR[8:0]$2864 9'xxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10247$14_ADDR[5:0]$2864 6'xxxxxx
     assign $0$memwr$\mem_1$ls180.v:10247$14_DATA[63:0]$2865 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_1$ls180.v:10247$14_EN[63:0]$2866 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_1$ls180.v:10245$13_ADDR[8:0]$2861 9'xxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10245$13_ADDR[5:0]$2861 6'xxxxxx
     assign $0$memwr$\mem_1$ls180.v:10245$13_DATA[63:0]$2862 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_1$ls180.v:10245$13_EN[63:0]$2863 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_1$ls180.v:10243$12_ADDR[8:0]$2858 9'xxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10243$12_ADDR[5:0]$2858 6'xxxxxx
     assign $0$memwr$\mem_1$ls180.v:10243$12_DATA[63:0]$2859 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_1$ls180.v:10243$12_EN[63:0]$2860 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_1$ls180.v:10241$11_ADDR[8:0]$2855 9'xxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10241$11_ADDR[5:0]$2855 6'xxxxxx
     assign $0$memwr$\mem_1$ls180.v:10241$11_DATA[63:0]$2856 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_1$ls180.v:10241$11_EN[63:0]$2857 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_1$ls180.v:10239$10_ADDR[8:0]$2852 9'xxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10239$10_ADDR[5:0]$2852 6'xxxxxx
     assign $0$memwr$\mem_1$ls180.v:10239$10_DATA[63:0]$2853 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_1$ls180.v:10239$10_EN[63:0]$2854 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_1$ls180.v:10237$9_ADDR[8:0]$2849 9'xxxxxxxxx
+    assign $0$memwr$\mem_1$ls180.v:10237$9_ADDR[5:0]$2849 6'xxxxxx
     assign $0$memwr$\mem_1$ls180.v:10237$9_DATA[63:0]$2850 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_1$ls180.v:10237$9_EN[63:0]$2851 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0\memadr_1[8:0] \main_sram0_adr
+    assign $0\memadr_1[5:0] \main_sram0_adr
     attribute \src "ls180.v:10236.2-10237.55"
     switch \main_sram0_we [0]
       attribute \src "ls180.v:10236.6-10236.22"
       case 1'1
-        assign $0$memwr$\mem_1$ls180.v:10237$9_ADDR[8:0]$2849 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10237$9_ADDR[5:0]$2849 \main_sram0_adr
         assign $0$memwr$\mem_1$ls180.v:10237$9_DATA[63:0]$2850 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] }
         assign $0$memwr$\mem_1$ls180.v:10237$9_EN[63:0]$2851 64'0000000000000000000000000000000000000000000000000000000011111111
       case 
@@ -265330,7 +265330,7 @@ module \ls180
     switch \main_sram0_we [1]
       attribute \src "ls180.v:10238.6-10238.22"
       case 1'1
-        assign $0$memwr$\mem_1$ls180.v:10239$10_ADDR[8:0]$2852 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10239$10_ADDR[5:0]$2852 \main_sram0_adr
         assign $0$memwr$\mem_1$ls180.v:10239$10_DATA[63:0]$2853 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx }
         assign $0$memwr$\mem_1$ls180.v:10239$10_EN[63:0]$2854 64'0000000000000000000000000000000000000000000000001111111100000000
       case 
@@ -265339,7 +265339,7 @@ module \ls180
     switch \main_sram0_we [2]
       attribute \src "ls180.v:10240.6-10240.22"
       case 1'1
-        assign $0$memwr$\mem_1$ls180.v:10241$11_ADDR[8:0]$2855 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10241$11_ADDR[5:0]$2855 \main_sram0_adr
         assign $0$memwr$\mem_1$ls180.v:10241$11_DATA[63:0]$2856 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_1$ls180.v:10241$11_EN[63:0]$2857 64'0000000000000000000000000000000000000000111111110000000000000000
       case 
@@ -265348,7 +265348,7 @@ module \ls180
     switch \main_sram0_we [3]
       attribute \src "ls180.v:10242.6-10242.22"
       case 1'1
-        assign $0$memwr$\mem_1$ls180.v:10243$12_ADDR[8:0]$2858 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10243$12_ADDR[5:0]$2858 \main_sram0_adr
         assign $0$memwr$\mem_1$ls180.v:10243$12_DATA[63:0]$2859 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_1$ls180.v:10243$12_EN[63:0]$2860 64'0000000000000000000000000000000011111111000000000000000000000000
       case 
@@ -265357,7 +265357,7 @@ module \ls180
     switch \main_sram0_we [4]
       attribute \src "ls180.v:10244.6-10244.22"
       case 1'1
-        assign $0$memwr$\mem_1$ls180.v:10245$13_ADDR[8:0]$2861 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10245$13_ADDR[5:0]$2861 \main_sram0_adr
         assign $0$memwr$\mem_1$ls180.v:10245$13_DATA[63:0]$2862 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_1$ls180.v:10245$13_EN[63:0]$2863 64'0000000000000000000000001111111100000000000000000000000000000000
       case 
@@ -265366,7 +265366,7 @@ module \ls180
     switch \main_sram0_we [5]
       attribute \src "ls180.v:10246.6-10246.22"
       case 1'1
-        assign $0$memwr$\mem_1$ls180.v:10247$14_ADDR[8:0]$2864 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10247$14_ADDR[5:0]$2864 \main_sram0_adr
         assign $0$memwr$\mem_1$ls180.v:10247$14_DATA[63:0]$2865 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_1$ls180.v:10247$14_EN[63:0]$2866 64'0000000000000000111111110000000000000000000000000000000000000000
       case 
@@ -265375,7 +265375,7 @@ module \ls180
     switch \main_sram0_we [6]
       attribute \src "ls180.v:10248.6-10248.22"
       case 1'1
-        assign $0$memwr$\mem_1$ls180.v:10249$15_ADDR[8:0]$2867 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10249$15_ADDR[5:0]$2867 \main_sram0_adr
         assign $0$memwr$\mem_1$ls180.v:10249$15_DATA[63:0]$2868 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_1$ls180.v:10249$15_EN[63:0]$2869 64'0000000011111111000000000000000000000000000000000000000000000000
       case 
@@ -265384,35 +265384,35 @@ module \ls180
     switch \main_sram0_we [7]
       attribute \src "ls180.v:10250.6-10250.22"
       case 1'1
-        assign $0$memwr$\mem_1$ls180.v:10251$16_ADDR[8:0]$2870 \main_sram0_adr
+        assign $0$memwr$\mem_1$ls180.v:10251$16_ADDR[5:0]$2870 \main_sram0_adr
         assign $0$memwr$\mem_1$ls180.v:10251$16_DATA[63:0]$2871 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_1$ls180.v:10251$16_EN[63:0]$2872 64'1111111100000000000000000000000000000000000000000000000000000000
       case 
     end
     sync posedge \sys_clk_1
-      update \memadr_1 $0\memadr_1[8:0]
-      update $memwr$\mem_1$ls180.v:10237$9_ADDR $0$memwr$\mem_1$ls180.v:10237$9_ADDR[8:0]$2849
+      update \memadr_1 $0\memadr_1[5:0]
+      update $memwr$\mem_1$ls180.v:10237$9_ADDR $0$memwr$\mem_1$ls180.v:10237$9_ADDR[5:0]$2849
       update $memwr$\mem_1$ls180.v:10237$9_DATA $0$memwr$\mem_1$ls180.v:10237$9_DATA[63:0]$2850
       update $memwr$\mem_1$ls180.v:10237$9_EN $0$memwr$\mem_1$ls180.v:10237$9_EN[63:0]$2851
-      update $memwr$\mem_1$ls180.v:10239$10_ADDR $0$memwr$\mem_1$ls180.v:10239$10_ADDR[8:0]$2852
+      update $memwr$\mem_1$ls180.v:10239$10_ADDR $0$memwr$\mem_1$ls180.v:10239$10_ADDR[5:0]$2852
       update $memwr$\mem_1$ls180.v:10239$10_DATA $0$memwr$\mem_1$ls180.v:10239$10_DATA[63:0]$2853
       update $memwr$\mem_1$ls180.v:10239$10_EN $0$memwr$\mem_1$ls180.v:10239$10_EN[63:0]$2854
-      update $memwr$\mem_1$ls180.v:10241$11_ADDR $0$memwr$\mem_1$ls180.v:10241$11_ADDR[8:0]$2855
+      update $memwr$\mem_1$ls180.v:10241$11_ADDR $0$memwr$\mem_1$ls180.v:10241$11_ADDR[5:0]$2855
       update $memwr$\mem_1$ls180.v:10241$11_DATA $0$memwr$\mem_1$ls180.v:10241$11_DATA[63:0]$2856
       update $memwr$\mem_1$ls180.v:10241$11_EN $0$memwr$\mem_1$ls180.v:10241$11_EN[63:0]$2857
-      update $memwr$\mem_1$ls180.v:10243$12_ADDR $0$memwr$\mem_1$ls180.v:10243$12_ADDR[8:0]$2858
+      update $memwr$\mem_1$ls180.v:10243$12_ADDR $0$memwr$\mem_1$ls180.v:10243$12_ADDR[5:0]$2858
       update $memwr$\mem_1$ls180.v:10243$12_DATA $0$memwr$\mem_1$ls180.v:10243$12_DATA[63:0]$2859
       update $memwr$\mem_1$ls180.v:10243$12_EN $0$memwr$\mem_1$ls180.v:10243$12_EN[63:0]$2860
-      update $memwr$\mem_1$ls180.v:10245$13_ADDR $0$memwr$\mem_1$ls180.v:10245$13_ADDR[8:0]$2861
+      update $memwr$\mem_1$ls180.v:10245$13_ADDR $0$memwr$\mem_1$ls180.v:10245$13_ADDR[5:0]$2861
       update $memwr$\mem_1$ls180.v:10245$13_DATA $0$memwr$\mem_1$ls180.v:10245$13_DATA[63:0]$2862
       update $memwr$\mem_1$ls180.v:10245$13_EN $0$memwr$\mem_1$ls180.v:10245$13_EN[63:0]$2863
-      update $memwr$\mem_1$ls180.v:10247$14_ADDR $0$memwr$\mem_1$ls180.v:10247$14_ADDR[8:0]$2864
+      update $memwr$\mem_1$ls180.v:10247$14_ADDR $0$memwr$\mem_1$ls180.v:10247$14_ADDR[5:0]$2864
       update $memwr$\mem_1$ls180.v:10247$14_DATA $0$memwr$\mem_1$ls180.v:10247$14_DATA[63:0]$2865
       update $memwr$\mem_1$ls180.v:10247$14_EN $0$memwr$\mem_1$ls180.v:10247$14_EN[63:0]$2866
-      update $memwr$\mem_1$ls180.v:10249$15_ADDR $0$memwr$\mem_1$ls180.v:10249$15_ADDR[8:0]$2867
+      update $memwr$\mem_1$ls180.v:10249$15_ADDR $0$memwr$\mem_1$ls180.v:10249$15_ADDR[5:0]$2867
       update $memwr$\mem_1$ls180.v:10249$15_DATA $0$memwr$\mem_1$ls180.v:10249$15_DATA[63:0]$2868
       update $memwr$\mem_1$ls180.v:10249$15_EN $0$memwr$\mem_1$ls180.v:10249$15_EN[63:0]$2869
-      update $memwr$\mem_1$ls180.v:10251$16_ADDR $0$memwr$\mem_1$ls180.v:10251$16_ADDR[8:0]$2870
+      update $memwr$\mem_1$ls180.v:10251$16_ADDR $0$memwr$\mem_1$ls180.v:10251$16_ADDR[5:0]$2870
       update $memwr$\mem_1$ls180.v:10251$16_DATA $0$memwr$\mem_1$ls180.v:10251$16_DATA[63:0]$2871
       update $memwr$\mem_1$ls180.v:10251$16_EN $0$memwr$\mem_1$ls180.v:10251$16_EN[63:0]$2872
   end
@@ -265459,36 +265459,36 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\mem_2$ls180.v:10279$24_ADDR[8:0]$2896 9'xxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10279$24_ADDR[5:0]$2896 6'xxxxxx
     assign $0$memwr$\mem_2$ls180.v:10279$24_DATA[63:0]$2897 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_2$ls180.v:10279$24_EN[63:0]$2898 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_2$ls180.v:10277$23_ADDR[8:0]$2893 9'xxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10277$23_ADDR[5:0]$2893 6'xxxxxx
     assign $0$memwr$\mem_2$ls180.v:10277$23_DATA[63:0]$2894 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_2$ls180.v:10277$23_EN[63:0]$2895 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_2$ls180.v:10275$22_ADDR[8:0]$2890 9'xxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10275$22_ADDR[5:0]$2890 6'xxxxxx
     assign $0$memwr$\mem_2$ls180.v:10275$22_DATA[63:0]$2891 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_2$ls180.v:10275$22_EN[63:0]$2892 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_2$ls180.v:10273$21_ADDR[8:0]$2887 9'xxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10273$21_ADDR[5:0]$2887 6'xxxxxx
     assign $0$memwr$\mem_2$ls180.v:10273$21_DATA[63:0]$2888 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_2$ls180.v:10273$21_EN[63:0]$2889 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_2$ls180.v:10271$20_ADDR[8:0]$2884 9'xxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10271$20_ADDR[5:0]$2884 6'xxxxxx
     assign $0$memwr$\mem_2$ls180.v:10271$20_DATA[63:0]$2885 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_2$ls180.v:10271$20_EN[63:0]$2886 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_2$ls180.v:10269$19_ADDR[8:0]$2881 9'xxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10269$19_ADDR[5:0]$2881 6'xxxxxx
     assign $0$memwr$\mem_2$ls180.v:10269$19_DATA[63:0]$2882 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_2$ls180.v:10269$19_EN[63:0]$2883 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_2$ls180.v:10267$18_ADDR[8:0]$2878 9'xxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10267$18_ADDR[5:0]$2878 6'xxxxxx
     assign $0$memwr$\mem_2$ls180.v:10267$18_DATA[63:0]$2879 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_2$ls180.v:10267$18_EN[63:0]$2880 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_2$ls180.v:10265$17_ADDR[8:0]$2875 9'xxxxxxxxx
+    assign $0$memwr$\mem_2$ls180.v:10265$17_ADDR[5:0]$2875 6'xxxxxx
     assign $0$memwr$\mem_2$ls180.v:10265$17_DATA[63:0]$2876 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_2$ls180.v:10265$17_EN[63:0]$2877 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0\memadr_2[8:0] \main_sram1_adr
+    assign $0\memadr_2[5:0] \main_sram1_adr
     attribute \src "ls180.v:10264.2-10265.55"
     switch \main_sram1_we [0]
       attribute \src "ls180.v:10264.6-10264.22"
       case 1'1
-        assign $0$memwr$\mem_2$ls180.v:10265$17_ADDR[8:0]$2875 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10265$17_ADDR[5:0]$2875 \main_sram1_adr
         assign $0$memwr$\mem_2$ls180.v:10265$17_DATA[63:0]$2876 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] }
         assign $0$memwr$\mem_2$ls180.v:10265$17_EN[63:0]$2877 64'0000000000000000000000000000000000000000000000000000000011111111
       case 
@@ -265497,7 +265497,7 @@ module \ls180
     switch \main_sram1_we [1]
       attribute \src "ls180.v:10266.6-10266.22"
       case 1'1
-        assign $0$memwr$\mem_2$ls180.v:10267$18_ADDR[8:0]$2878 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10267$18_ADDR[5:0]$2878 \main_sram1_adr
         assign $0$memwr$\mem_2$ls180.v:10267$18_DATA[63:0]$2879 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx }
         assign $0$memwr$\mem_2$ls180.v:10267$18_EN[63:0]$2880 64'0000000000000000000000000000000000000000000000001111111100000000
       case 
@@ -265506,7 +265506,7 @@ module \ls180
     switch \main_sram1_we [2]
       attribute \src "ls180.v:10268.6-10268.22"
       case 1'1
-        assign $0$memwr$\mem_2$ls180.v:10269$19_ADDR[8:0]$2881 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10269$19_ADDR[5:0]$2881 \main_sram1_adr
         assign $0$memwr$\mem_2$ls180.v:10269$19_DATA[63:0]$2882 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_2$ls180.v:10269$19_EN[63:0]$2883 64'0000000000000000000000000000000000000000111111110000000000000000
       case 
@@ -265515,7 +265515,7 @@ module \ls180
     switch \main_sram1_we [3]
       attribute \src "ls180.v:10270.6-10270.22"
       case 1'1
-        assign $0$memwr$\mem_2$ls180.v:10271$20_ADDR[8:0]$2884 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10271$20_ADDR[5:0]$2884 \main_sram1_adr
         assign $0$memwr$\mem_2$ls180.v:10271$20_DATA[63:0]$2885 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_2$ls180.v:10271$20_EN[63:0]$2886 64'0000000000000000000000000000000011111111000000000000000000000000
       case 
@@ -265524,7 +265524,7 @@ module \ls180
     switch \main_sram1_we [4]
       attribute \src "ls180.v:10272.6-10272.22"
       case 1'1
-        assign $0$memwr$\mem_2$ls180.v:10273$21_ADDR[8:0]$2887 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10273$21_ADDR[5:0]$2887 \main_sram1_adr
         assign $0$memwr$\mem_2$ls180.v:10273$21_DATA[63:0]$2888 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_2$ls180.v:10273$21_EN[63:0]$2889 64'0000000000000000000000001111111100000000000000000000000000000000
       case 
@@ -265533,7 +265533,7 @@ module \ls180
     switch \main_sram1_we [5]
       attribute \src "ls180.v:10274.6-10274.22"
       case 1'1
-        assign $0$memwr$\mem_2$ls180.v:10275$22_ADDR[8:0]$2890 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10275$22_ADDR[5:0]$2890 \main_sram1_adr
         assign $0$memwr$\mem_2$ls180.v:10275$22_DATA[63:0]$2891 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_2$ls180.v:10275$22_EN[63:0]$2892 64'0000000000000000111111110000000000000000000000000000000000000000
       case 
@@ -265542,7 +265542,7 @@ module \ls180
     switch \main_sram1_we [6]
       attribute \src "ls180.v:10276.6-10276.22"
       case 1'1
-        assign $0$memwr$\mem_2$ls180.v:10277$23_ADDR[8:0]$2893 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10277$23_ADDR[5:0]$2893 \main_sram1_adr
         assign $0$memwr$\mem_2$ls180.v:10277$23_DATA[63:0]$2894 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_2$ls180.v:10277$23_EN[63:0]$2895 64'0000000011111111000000000000000000000000000000000000000000000000
       case 
@@ -265551,35 +265551,35 @@ module \ls180
     switch \main_sram1_we [7]
       attribute \src "ls180.v:10278.6-10278.22"
       case 1'1
-        assign $0$memwr$\mem_2$ls180.v:10279$24_ADDR[8:0]$2896 \main_sram1_adr
+        assign $0$memwr$\mem_2$ls180.v:10279$24_ADDR[5:0]$2896 \main_sram1_adr
         assign $0$memwr$\mem_2$ls180.v:10279$24_DATA[63:0]$2897 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_2$ls180.v:10279$24_EN[63:0]$2898 64'1111111100000000000000000000000000000000000000000000000000000000
       case 
     end
     sync posedge \sys_clk_1
-      update \memadr_2 $0\memadr_2[8:0]
-      update $memwr$\mem_2$ls180.v:10265$17_ADDR $0$memwr$\mem_2$ls180.v:10265$17_ADDR[8:0]$2875
+      update \memadr_2 $0\memadr_2[5:0]
+      update $memwr$\mem_2$ls180.v:10265$17_ADDR $0$memwr$\mem_2$ls180.v:10265$17_ADDR[5:0]$2875
       update $memwr$\mem_2$ls180.v:10265$17_DATA $0$memwr$\mem_2$ls180.v:10265$17_DATA[63:0]$2876
       update $memwr$\mem_2$ls180.v:10265$17_EN $0$memwr$\mem_2$ls180.v:10265$17_EN[63:0]$2877
-      update $memwr$\mem_2$ls180.v:10267$18_ADDR $0$memwr$\mem_2$ls180.v:10267$18_ADDR[8:0]$2878
+      update $memwr$\mem_2$ls180.v:10267$18_ADDR $0$memwr$\mem_2$ls180.v:10267$18_ADDR[5:0]$2878
       update $memwr$\mem_2$ls180.v:10267$18_DATA $0$memwr$\mem_2$ls180.v:10267$18_DATA[63:0]$2879
       update $memwr$\mem_2$ls180.v:10267$18_EN $0$memwr$\mem_2$ls180.v:10267$18_EN[63:0]$2880
-      update $memwr$\mem_2$ls180.v:10269$19_ADDR $0$memwr$\mem_2$ls180.v:10269$19_ADDR[8:0]$2881
+      update $memwr$\mem_2$ls180.v:10269$19_ADDR $0$memwr$\mem_2$ls180.v:10269$19_ADDR[5:0]$2881
       update $memwr$\mem_2$ls180.v:10269$19_DATA $0$memwr$\mem_2$ls180.v:10269$19_DATA[63:0]$2882
       update $memwr$\mem_2$ls180.v:10269$19_EN $0$memwr$\mem_2$ls180.v:10269$19_EN[63:0]$2883
-      update $memwr$\mem_2$ls180.v:10271$20_ADDR $0$memwr$\mem_2$ls180.v:10271$20_ADDR[8:0]$2884
+      update $memwr$\mem_2$ls180.v:10271$20_ADDR $0$memwr$\mem_2$ls180.v:10271$20_ADDR[5:0]$2884
       update $memwr$\mem_2$ls180.v:10271$20_DATA $0$memwr$\mem_2$ls180.v:10271$20_DATA[63:0]$2885
       update $memwr$\mem_2$ls180.v:10271$20_EN $0$memwr$\mem_2$ls180.v:10271$20_EN[63:0]$2886
-      update $memwr$\mem_2$ls180.v:10273$21_ADDR $0$memwr$\mem_2$ls180.v:10273$21_ADDR[8:0]$2887
+      update $memwr$\mem_2$ls180.v:10273$21_ADDR $0$memwr$\mem_2$ls180.v:10273$21_ADDR[5:0]$2887
       update $memwr$\mem_2$ls180.v:10273$21_DATA $0$memwr$\mem_2$ls180.v:10273$21_DATA[63:0]$2888
       update $memwr$\mem_2$ls180.v:10273$21_EN $0$memwr$\mem_2$ls180.v:10273$21_EN[63:0]$2889
-      update $memwr$\mem_2$ls180.v:10275$22_ADDR $0$memwr$\mem_2$ls180.v:10275$22_ADDR[8:0]$2890
+      update $memwr$\mem_2$ls180.v:10275$22_ADDR $0$memwr$\mem_2$ls180.v:10275$22_ADDR[5:0]$2890
       update $memwr$\mem_2$ls180.v:10275$22_DATA $0$memwr$\mem_2$ls180.v:10275$22_DATA[63:0]$2891
       update $memwr$\mem_2$ls180.v:10275$22_EN $0$memwr$\mem_2$ls180.v:10275$22_EN[63:0]$2892
-      update $memwr$\mem_2$ls180.v:10277$23_ADDR $0$memwr$\mem_2$ls180.v:10277$23_ADDR[8:0]$2893
+      update $memwr$\mem_2$ls180.v:10277$23_ADDR $0$memwr$\mem_2$ls180.v:10277$23_ADDR[5:0]$2893
       update $memwr$\mem_2$ls180.v:10277$23_DATA $0$memwr$\mem_2$ls180.v:10277$23_DATA[63:0]$2894
       update $memwr$\mem_2$ls180.v:10277$23_EN $0$memwr$\mem_2$ls180.v:10277$23_EN[63:0]$2895
-      update $memwr$\mem_2$ls180.v:10279$24_ADDR $0$memwr$\mem_2$ls180.v:10279$24_ADDR[8:0]$2896
+      update $memwr$\mem_2$ls180.v:10279$24_ADDR $0$memwr$\mem_2$ls180.v:10279$24_ADDR[5:0]$2896
       update $memwr$\mem_2$ls180.v:10279$24_DATA $0$memwr$\mem_2$ls180.v:10279$24_DATA[63:0]$2897
       update $memwr$\mem_2$ls180.v:10279$24_EN $0$memwr$\mem_2$ls180.v:10279$24_EN[63:0]$2898
   end
@@ -265626,36 +265626,36 @@ module \ls180
     assign { } { }
     assign { } { }
     assign { } { }
-    assign $0$memwr$\mem_3$ls180.v:10307$32_ADDR[8:0]$2922 9'xxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10307$32_ADDR[5:0]$2922 6'xxxxxx
     assign $0$memwr$\mem_3$ls180.v:10307$32_DATA[63:0]$2923 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_3$ls180.v:10307$32_EN[63:0]$2924 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_3$ls180.v:10305$31_ADDR[8:0]$2919 9'xxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10305$31_ADDR[5:0]$2919 6'xxxxxx
     assign $0$memwr$\mem_3$ls180.v:10305$31_DATA[63:0]$2920 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_3$ls180.v:10305$31_EN[63:0]$2921 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_3$ls180.v:10303$30_ADDR[8:0]$2916 9'xxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10303$30_ADDR[5:0]$2916 6'xxxxxx
     assign $0$memwr$\mem_3$ls180.v:10303$30_DATA[63:0]$2917 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_3$ls180.v:10303$30_EN[63:0]$2918 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_3$ls180.v:10301$29_ADDR[8:0]$2913 9'xxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10301$29_ADDR[5:0]$2913 6'xxxxxx
     assign $0$memwr$\mem_3$ls180.v:10301$29_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_3$ls180.v:10301$29_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_3$ls180.v:10299$28_ADDR[8:0]$2910 9'xxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10299$28_ADDR[5:0]$2910 6'xxxxxx
     assign $0$memwr$\mem_3$ls180.v:10299$28_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_3$ls180.v:10299$28_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_3$ls180.v:10297$27_ADDR[8:0]$2907 9'xxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10297$27_ADDR[5:0]$2907 6'xxxxxx
     assign $0$memwr$\mem_3$ls180.v:10297$27_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_3$ls180.v:10297$27_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_3$ls180.v:10295$26_ADDR[8:0]$2904 9'xxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10295$26_ADDR[5:0]$2904 6'xxxxxx
     assign $0$memwr$\mem_3$ls180.v:10295$26_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_3$ls180.v:10295$26_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0$memwr$\mem_3$ls180.v:10293$25_ADDR[8:0]$2901 9'xxxxxxxxx
+    assign $0$memwr$\mem_3$ls180.v:10293$25_ADDR[5:0]$2901 6'xxxxxx
     assign $0$memwr$\mem_3$ls180.v:10293$25_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
     assign $0$memwr$\mem_3$ls180.v:10293$25_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign $0\memadr_3[8:0] \main_sram2_adr
+    assign $0\memadr_3[5:0] \main_sram2_adr
     attribute \src "ls180.v:10292.2-10293.55"
     switch \main_sram2_we [0]
       attribute \src "ls180.v:10292.6-10292.22"
       case 1'1
-        assign $0$memwr$\mem_3$ls180.v:10293$25_ADDR[8:0]$2901 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10293$25_ADDR[5:0]$2901 \main_sram2_adr
         assign $0$memwr$\mem_3$ls180.v:10293$25_DATA[63:0]$2902 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] }
         assign $0$memwr$\mem_3$ls180.v:10293$25_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000011111111
       case 
@@ -265664,7 +265664,7 @@ module \ls180
     switch \main_sram2_we [1]
       attribute \src "ls180.v:10294.6-10294.22"
       case 1'1
-        assign $0$memwr$\mem_3$ls180.v:10295$26_ADDR[8:0]$2904 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10295$26_ADDR[5:0]$2904 \main_sram2_adr
         assign $0$memwr$\mem_3$ls180.v:10295$26_DATA[63:0]$2905 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx }
         assign $0$memwr$\mem_3$ls180.v:10295$26_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000001111111100000000
       case 
@@ -265673,7 +265673,7 @@ module \ls180
     switch \main_sram2_we [2]
       attribute \src "ls180.v:10296.6-10296.22"
       case 1'1
-        assign $0$memwr$\mem_3$ls180.v:10297$27_ADDR[8:0]$2907 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10297$27_ADDR[5:0]$2907 \main_sram2_adr
         assign $0$memwr$\mem_3$ls180.v:10297$27_DATA[63:0]$2908 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_3$ls180.v:10297$27_EN[63:0]$2909 64'0000000000000000000000000000000000000000111111110000000000000000
       case 
@@ -265682,7 +265682,7 @@ module \ls180
     switch \main_sram2_we [3]
       attribute \src "ls180.v:10298.6-10298.22"
       case 1'1
-        assign $0$memwr$\mem_3$ls180.v:10299$28_ADDR[8:0]$2910 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10299$28_ADDR[5:0]$2910 \main_sram2_adr
         assign $0$memwr$\mem_3$ls180.v:10299$28_DATA[63:0]$2911 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_3$ls180.v:10299$28_EN[63:0]$2912 64'0000000000000000000000000000000011111111000000000000000000000000
       case 
@@ -265691,7 +265691,7 @@ module \ls180
     switch \main_sram2_we [4]
       attribute \src "ls180.v:10300.6-10300.22"
       case 1'1
-        assign $0$memwr$\mem_3$ls180.v:10301$29_ADDR[8:0]$2913 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10301$29_ADDR[5:0]$2913 \main_sram2_adr
         assign $0$memwr$\mem_3$ls180.v:10301$29_DATA[63:0]$2914 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_3$ls180.v:10301$29_EN[63:0]$2915 64'0000000000000000000000001111111100000000000000000000000000000000
       case 
@@ -265700,7 +265700,7 @@ module \ls180
     switch \main_sram2_we [5]
       attribute \src "ls180.v:10302.6-10302.22"
       case 1'1
-        assign $0$memwr$\mem_3$ls180.v:10303$30_ADDR[8:0]$2916 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10303$30_ADDR[5:0]$2916 \main_sram2_adr
         assign $0$memwr$\mem_3$ls180.v:10303$30_DATA[63:0]$2917 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_3$ls180.v:10303$30_EN[63:0]$2918 64'0000000000000000111111110000000000000000000000000000000000000000
       case 
@@ -265709,7 +265709,7 @@ module \ls180
     switch \main_sram2_we [6]
       attribute \src "ls180.v:10304.6-10304.22"
       case 1'1
-        assign $0$memwr$\mem_3$ls180.v:10305$31_ADDR[8:0]$2919 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10305$31_ADDR[5:0]$2919 \main_sram2_adr
         assign $0$memwr$\mem_3$ls180.v:10305$31_DATA[63:0]$2920 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_3$ls180.v:10305$31_EN[63:0]$2921 64'0000000011111111000000000000000000000000000000000000000000000000
       case 
@@ -265718,35 +265718,35 @@ module \ls180
     switch \main_sram2_we [7]
       attribute \src "ls180.v:10306.6-10306.22"
       case 1'1
-        assign $0$memwr$\mem_3$ls180.v:10307$32_ADDR[8:0]$2922 \main_sram2_adr
+        assign $0$memwr$\mem_3$ls180.v:10307$32_ADDR[5:0]$2922 \main_sram2_adr
         assign $0$memwr$\mem_3$ls180.v:10307$32_DATA[63:0]$2923 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx }
         assign $0$memwr$\mem_3$ls180.v:10307$32_EN[63:0]$2924 64'1111111100000000000000000000000000000000000000000000000000000000
       case 
     end
     sync posedge \sys_clk_1
-      update \memadr_3 $0\memadr_3[8:0]
-      update $memwr$\mem_3$ls180.v:10293$25_ADDR $0$memwr$\mem_3$ls180.v:10293$25_ADDR[8:0]$2901
+      update \memadr_3 $0\memadr_3[5:0]
+      update $memwr$\mem_3$ls180.v:10293$25_ADDR $0$memwr$\mem_3$ls180.v:10293$25_ADDR[5:0]$2901
       update $memwr$\mem_3$ls180.v:10293$25_DATA $0$memwr$\mem_3$ls180.v:10293$25_DATA[63:0]$2902
       update $memwr$\mem_3$ls180.v:10293$25_EN $0$memwr$\mem_3$ls180.v:10293$25_EN[63:0]$2903
-      update $memwr$\mem_3$ls180.v:10295$26_ADDR $0$memwr$\mem_3$ls180.v:10295$26_ADDR[8:0]$2904
+      update $memwr$\mem_3$ls180.v:10295$26_ADDR $0$memwr$\mem_3$ls180.v:10295$26_ADDR[5:0]$2904
       update $memwr$\mem_3$ls180.v:10295$26_DATA $0$memwr$\mem_3$ls180.v:10295$26_DATA[63:0]$2905
       update $memwr$\mem_3$ls180.v:10295$26_EN $0$memwr$\mem_3$ls180.v:10295$26_EN[63:0]$2906
-      update $memwr$\mem_3$ls180.v:10297$27_ADDR $0$memwr$\mem_3$ls180.v:10297$27_ADDR[8:0]$2907
+      update $memwr$\mem_3$ls180.v:10297$27_ADDR $0$memwr$\mem_3$ls180.v:10297$27_ADDR[5:0]$2907
       update $memwr$\mem_3$ls180.v:10297$27_DATA $0$memwr$\mem_3$ls180.v:10297$27_DATA[63:0]$2908
       update $memwr$\mem_3$ls180.v:10297$27_EN $0$memwr$\mem_3$ls180.v:10297$27_EN[63:0]$2909
-      update $memwr$\mem_3$ls180.v:10299$28_ADDR $0$memwr$\mem_3$ls180.v:10299$28_ADDR[8:0]$2910
+      update $memwr$\mem_3$ls180.v:10299$28_ADDR $0$memwr$\mem_3$ls180.v:10299$28_ADDR[5:0]$2910
       update $memwr$\mem_3$ls180.v:10299$28_DATA $0$memwr$\mem_3$ls180.v:10299$28_DATA[63:0]$2911
       update $memwr$\mem_3$ls180.v:10299$28_EN $0$memwr$\mem_3$ls180.v:10299$28_EN[63:0]$2912
-      update $memwr$\mem_3$ls180.v:10301$29_ADDR $0$memwr$\mem_3$ls180.v:10301$29_ADDR[8:0]$2913
+      update $memwr$\mem_3$ls180.v:10301$29_ADDR $0$memwr$\mem_3$ls180.v:10301$29_ADDR[5:0]$2913
       update $memwr$\mem_3$ls180.v:10301$29_DATA $0$memwr$\mem_3$ls180.v:10301$29_DATA[63:0]$2914
       update $memwr$\mem_3$ls180.v:10301$29_EN $0$memwr$\mem_3$ls180.v:10301$29_EN[63:0]$2915
-      update $memwr$\mem_3$ls180.v:10303$30_ADDR $0$memwr$\mem_3$ls180.v:10303$30_ADDR[8:0]$2916
+      update $memwr$\mem_3$ls180.v:10303$30_ADDR $0$memwr$\mem_3$ls180.v:10303$30_ADDR[5:0]$2916
       update $memwr$\mem_3$ls180.v:10303$30_DATA $0$memwr$\mem_3$ls180.v:10303$30_DATA[63:0]$2917
       update $memwr$\mem_3$ls180.v:10303$30_EN $0$memwr$\mem_3$ls180.v:10303$30_EN[63:0]$2918
-      update $memwr$\mem_3$ls180.v:10305$31_ADDR $0$memwr$\mem_3$ls180.v:10305$31_ADDR[8:0]$2919
+      update $memwr$\mem_3$ls180.v:10305$31_ADDR $0$memwr$\mem_3$ls180.v:10305$31_ADDR[5:0]$2919
       update $memwr$\mem_3$ls180.v:10305$31_DATA $0$memwr$\mem_3$ls180.v:10305$31_DATA[63:0]$2920
       update $memwr$\mem_3$ls180.v:10305$31_EN $0$memwr$\mem_3$ls180.v:10305$31_EN[63:0]$2921
-      update $memwr$\mem_3$ls180.v:10307$32_ADDR $0$memwr$\mem_3$ls180.v:10307$32_ADDR[8:0]$2922
+      update $memwr$\mem_3$ls180.v:10307$32_ADDR $0$memwr$\mem_3$ls180.v:10307$32_ADDR[5:0]$2922
       update $memwr$\mem_3$ls180.v:10307$32_DATA $0$memwr$\mem_3$ls180.v:10307$32_DATA[63:0]$2923
       update $memwr$\mem_3$ls180.v:10307$32_EN $0$memwr$\mem_3$ls180.v:10307$32_EN[63:0]$2924
   end
@@ -277848,14 +277848,14 @@ module \ls180
   end
   attribute \src "ls180.v:7564.1-10203.4"
   process $proc$ls180.v:7564$2507
+    assign $0\uart_tx[0:0] \uart_tx
     assign $0\spisdcard_clk[0:0] \spisdcard_clk
     assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
     assign { } { }
-    assign $0\uart_tx[0:0] \uart_tx
-    assign $0\pwm[1:0] \pwm
     assign $0\spimaster_clk[0:0] \spimaster_clk
     assign $0\spimaster_mosi[0:0] \spimaster_mosi
     assign { } { }
+    assign $0\pwm[1:0] \pwm
     assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
     assign { } { }
     assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
@@ -282419,14 +282419,14 @@ module \ls180
         assign $0\main_libresocsim_scratch_storage[31:0] 305419896
         assign $0\main_libresocsim_scratch_re[0:0] 1'0
         assign $0\main_libresocsim_bus_errors[31:0] 0
+        assign $0\uart_tx[0:0] 1'1
         assign $0\spisdcard_clk[0:0] 1'0
         assign $0\spisdcard_mosi[0:0] 1'0
         assign $0\spisdcard_cs_n[0:0] 1'0
-        assign $0\uart_tx[0:0] 1'1
-        assign $0\pwm[1:0] 2'00
         assign $0\spimaster_clk[0:0] 1'0
         assign $0\spimaster_mosi[0:0] 1'0
         assign $0\spimaster_cs_n[0:0] 1'0
+        assign $0\pwm[1:0] 2'00
         assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0
         assign $0\main_libresocsim_load_storage[31:0] 0
         assign $0\main_libresocsim_load_re[0:0] 1'0
@@ -282713,14 +282713,14 @@ module \ls180
       case 
     end
     sync posedge \sys_clk_1
+      update \uart_tx $0\uart_tx[0:0]
       update \spisdcard_clk $0\spisdcard_clk[0:0]
       update \spisdcard_mosi $0\spisdcard_mosi[0:0]
       update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
-      update \uart_tx $0\uart_tx[0:0]
-      update \pwm $0\pwm[1:0]
       update \spimaster_clk $0\spimaster_clk[0:0]
       update \spimaster_mosi $0\spimaster_mosi[0:0]
       update \spimaster_cs_n $0\spimaster_cs_n[0:0]
+      update \pwm $0\pwm[1:0]
       update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
       update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
       update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
@@ -284037,7 +284037,7 @@ module \ls180
   connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] }
   connect \main_libresocsim_reset \main_libresocsim_reset_re
   connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors
-  connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [8:0]
+  connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0]
   connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r
   connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w
   connect \main_libresocsim_zero_trigger $ne$ls180.v:3021$100_Y
@@ -284045,13 +284045,13 @@ module \ls180
   connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending
   connect \main_libresocsim_irq $and$ls180.v:3030$103_Y
   connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger
-  connect \main_sram0_adr \main_interface0_ram_bus_adr [8:0]
+  connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0]
   connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r
   connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w
-  connect \main_sram1_adr \main_interface1_ram_bus_adr [8:0]
+  connect \main_sram1_adr \main_interface1_ram_bus_adr [5:0]
   connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r
   connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w
-  connect \main_sram2_adr \main_interface2_ram_bus_adr [8:0]
+  connect \main_sram2_adr \main_interface2_ram_bus_adr [5:0]
   connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r
   connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w
   connect \sys_clk_1 \sys_clk