add UART reserved IRQ @ 0
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 4 Sep 2020 19:56:44 +0000 (20:56 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 4 Sep 2020 19:56:44 +0000 (20:56 +0100)
commit6b85a4cdca82b820697ee07ac01d37673e26528d
tree9986963b42b84814265060921861de0d16278ebb
parent5ce5507af3cfb53c1e8f0417dc754172492bbe6e
add UART reserved IRQ @ 0
src/soc/litex/florent/sim.py