rename sys_clk in adder test experiments10_verilog (success compile)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 10:56:53 +0000 (10:56 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 12 Apr 2021 10:56:53 +0000 (10:56 +0000)
commit85d5e4f8d37b2c7d9a419d12cc585a35b386c49f
treef1f02d6922bbae70f6d1f46c7c4fd479356270d3
parent5da6eed52e9eeb94001f98d18469e1692125ce9f
rename sys_clk in adder test experiments10_verilog (success compile)
experiments10_verilog/add.py
experiments10_verilog/coriolis2/settings.py
experiments10_verilog/doDesign.py