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(parent: 7d76126) | patch
wishbone.bus: add Interface.
authorwhitequark <whitequark@whitequark.org>
Fri, 25 Oct 2019 21:22:59 +0000 (21:22 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 25 Oct 2019 21:30:56 +0000 (21:30 +0000)
commit8662815e1ea67341cdbcb3fdb77faccd1ed73cfd
treebb78b0d72cb693cd39b3179001b9b9902e9aa80dtree
parent7d76126fecd25d4242e64f14728041f760c4fac3commit | diff
wishbone.bus: add Interface.
nmigen_soc/csr/bus.py diff | blob | history
nmigen_soc/test/test_csr_bus.py diff | blob | history
nmigen_soc/test/test_wishbone_bus.py [new file with mode: 0644] blob
nmigen_soc/wishbone/__init__.py [new file with mode: 0644] blob
nmigen_soc/wishbone/bus.py [new file with mode: 0644] blob