add "nocore" option to build verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 28 Sep 2020 11:27:34 +0000 (12:27 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 28 Sep 2020 11:33:37 +0000 (12:33 +0100)
commit911b4858ff2fb8cf605bc0b530269182f7a6f5a9
tree47c1a1ef09f02d5beaaa8fab76f308b8a0f65e5b
parentc0c549dbb052e8ee34a874008c79c2752e3af749
add "nocore" option to build verilog
src/soc/simple/core.py
src/soc/simple/issuer_verilog.py