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(parent: ac472d9) | patch
add extra (test dummy stage in trap to see if combinatorial latency is reduced
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 16 Oct 2020 18:09:40 +0000 (19:09 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 16 Oct 2020 18:09:40 +0000 (19:09 +0100)
commit9fa4a517dc3f1fccac123de57f6c856e530f7ceb
tree937eea3adf961821483fcecf127be097b803492ftree
parentac472d93faad1d1082ad8436fdf52a4b052000b2commit | diff
add extra (test dummy stage in trap to see if combinatorial latency is reduced
src/soc/fu/trap/pipeline.py diff | blob | history