add extra (test dummy stage in trap to see if combinatorial latency is reduced
[soc.git] / src / soc / fu / trap / pipeline.py
1 from nmutil.singlepipe import ControlBase
2 from nmutil.pipemodbase import PipeModBaseChain
3 from soc.fu.trap.main_stage import TrapMainStage
4 from soc.fu.trap.pipe_data import TrapOutputData
5 from nmutil.pipemodbase import PipeModBase
6 from nmigen import Module
7
8 # gives a 1-clock delay to stop combinatorial link between in and out
9 class DummyTrapStage(PipeModBase):
10 def __init__(self, pspec): super().__init__(pspec, "dummy")
11 def ispec(self): return TrapOutputData(self.pspec)
12 def ospec(self): return TrapOutputData(self.pspec)
13
14 def elaborate(self, platform):
15 m = Module()
16 m.d.comb += self.o.eq(self.i) # pass-through output
17 return m
18
19
20 class TrapDummyStages(PipeModBaseChain):
21 def get_chain(self):
22 dummy = DummyTrapStage(self.pspec)
23 return [dummy]
24
25
26 class TrapStages(PipeModBaseChain):
27 def get_chain(self):
28 main = TrapMainStage(self.pspec)
29 return [main]
30
31
32 class TrapBasePipe(ControlBase):
33 def __init__(self, pspec):
34 ControlBase.__init__(self)
35 self.pspec = pspec
36 self.pipe1 = TrapStages(pspec)
37 self.pipe2 = TrapDummyStages(pspec)
38 self._eqs = self.connect([self.pipe1, self.pipe2])
39
40 def elaborate(self, platform):
41 m = ControlBase.elaborate(self, platform)
42 m.submodules.pipe1 = self.pipe1
43 m.submodules.pipe2 = self.pipe2
44 m.d.comb += self._eqs
45 return m