give module appropriate top-level name in microwatt compat mode
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 3 Jan 2022 22:10:17 +0000 (22:10 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 3 Jan 2022 22:10:17 +0000 (22:10 +0000)
commitc35433591d902d6f487b7d9a298925e2475c96db
treefc8b3066c2ac60a643742642e45d294ca389eb82
parent72f4dbcc231be82058bf13af4800fcb260867de5
give module appropriate top-level name in microwatt compat mode
src/soc/simple/issuer_verilog.py