add way to bypass PLL for ECP5 and sim
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 11 Oct 2020 15:01:58 +0000 (16:01 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 11 Oct 2020 15:01:58 +0000 (16:01 +0100)
commitc47427ce770a8b59c3e47a7e37fdbc30c959ab53
treeff461184186131754d60f386d9b69e697de3c828
parent02669870b503ce4832c9343bf17fce579ec49daf
add way to bypass PLL for ECP5 and sim
src/soc/simple/issuer.py
src/soc/simple/issuer_verilog.py