use soc.bus.sram instead of nmigen_soc.wishbone.sram
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 20 Apr 2021 14:37:24 +0000 (15:37 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 20 Apr 2021 14:37:24 +0000 (15:37 +0100)
commitc8ad3d01dff5b258ac72d96e91ea6ebc478e5505
treef9ada5e3f4069e925658ce43a5517292488c4ac3
parent5335aad7de728afb53e4fe89fe93fbccbdee1cff
use soc.bus.sram instead of nmigen_soc.wishbone.sram
src/soc/bus/test/test_minerva.py
src/soc/bus/test/test_sram_wb_downconvert.py
src/soc/bus/test/test_sram_wishbone.py
src/soc/debug/dmi2jtag.py
src/soc/debug/firmware_upload.py
src/soc/debug/test/test_jtag_tap.py
src/soc/debug/test/test_jtag_tap_srv.py
src/soc/experiment/dcache.py
src/soc/experiment/icache.py