sorting out missing clock somewhere
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 15 Oct 2020 17:05:44 +0000 (18:05 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 15 Oct 2020 17:05:44 +0000 (18:05 +0100)
commitcd691b9c5485c1898be80dc773f52120f8768698
treee99c4ff64f21e6657e2b7f4b66272eba337f0c0c
parentd22f6e2ecd3831f5662e9b78ad51731418c343b2
sorting out missing clock somewhere
src/soc/simple/core.py
src/soc/simple/issuer.py
src/soc/simple/issuer_verilog.py