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(parent: 2e1df6a) | patch
nir: Add options to nir_lower_compute_system_values to control compute ID base lowering
authorJesse Natalie <jenatali@microsoft.com>
Fri, 21 Aug 2020 17:40:45 +0000 (10:40 -0700)
committerMarge Bot <eric+marge@anholt.net>
Fri, 21 Aug 2020 22:07:05 +0000 (22:07 +0000)
commitd3faac7a155969722cd5c1e7806c141762c39757
treef3aaae6cd1bd4df53ee085c160a0e4aee9abeeebtree
parent2e1df6a17ff82c4a456caa8be4bfae1fac009b6acommit | diff
nir: Add options to nir_lower_compute_system_values to control compute ID base lowering

If no options are provided, existing intrinsics are used.
If the lowering pass indicates there should be offsets used for global
invocation ID or work group ID, then those instructions are lowered to
include the offset.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5891>
13 files changed:
src/amd/vulkan/radv_shader.c diff | blob | history
src/broadcom/compiler/vir.c diff | blob | history
src/compiler/nir/nir.h diff | blob | history
src/compiler/nir/nir_lower_system_values.c diff | blob | history
src/freedreno/vulkan/tu_shader.c diff | blob | history
src/gallium/auxiliary/nir/tgsi_to_nir.c diff | blob | history
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c diff | blob | history
src/gallium/frontends/clover/nir/invocation.cpp diff | blob | history
src/gallium/frontends/vallium/val_pipeline.c diff | blob | history
src/intel/compiler/brw_nir.c diff | blob | history
src/mesa/state_tracker/st_glsl_to_nir.cpp diff | blob | history
src/mesa/state_tracker/st_nir_builtins.c diff | blob | history
src/mesa/state_tracker/st_program.c diff | blob | history