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(parent: 3588ef2) | patch
output registers need to be Data type (consistently)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 24 May 2020 12:01:50 +0000 (13:01 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 24 May 2020 12:01:50 +0000 (13:01 +0100)
commitf43d91bdbfcad92e317722acb78864b78cf7bd77
tree24421a22fa1ed3f2476d28addec35bffeb39e0a8tree
parent3588ef20ea852726a5b421fd17dba586a7f491c0commit | diff
output registers need to be Data type (consistently)
src/soc/fu/alu/pipe_data.py diff | blob | history
src/soc/fu/cr/pipe_data.py diff | blob | history
src/soc/fu/logical/pipe_data.py diff | blob | history