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add jtag interface to issuer_verilog
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 22 Sep 2020 12:01:00 +0000
(13:01 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 22 Sep 2020 12:01:00 +0000
(13:01 +0100)
src/soc/debug/dmi.py
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src/soc/debug/dmi2jtag.py
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src/soc/debug/jtag.py
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src/soc/simple/issuer.py
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src/soc/simple/issuer_verilog.py
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diff --git
a/src/soc/debug/dmi.py
b/src/soc/debug/dmi.py
index 5875813cd4ade09ed0e7562f666b87d0061f954d..39ea799b4da63acddc2081818c2eb0e853327968 100644
(file)
--- a/
src/soc/debug/dmi.py
+++ b/
src/soc/debug/dmi.py
@@
-61,6
+61,14
@@
class DMIInterface(RecordObject):
self.we_i = Signal() # DMI write-enable
self.ack_o = Signal() # DMI ack request
self.we_i = Signal() # DMI write-enable
self.ack_o = Signal() # DMI ack request
+ def connect_to(self, other):
+ return [self.addr_i.eq(other.addr_i),
+ self.req_i.eq(other.req_i),
+ self.we_i.eq(other.we_i),
+ self.din.eq(other.din),
+ other.ack_o.eq(self.ack_o),
+ other.dout.eq(self.dout),
+ ]
class DbgReg(RecordObject):
def __init__(self, name):
class DbgReg(RecordObject):
def __init__(self, name):
diff --git
a/src/soc/debug/dmi2jtag.py
b/src/soc/debug/dmi2jtag.py
index d178c14a9ce1f681b1f6c35af97c8eccce1814ac..96b13b2d382d69e0aaa1c311638a0827ffd16ca7 100644
(file)
--- a/
src/soc/debug/dmi2jtag.py
+++ b/
src/soc/debug/dmi2jtag.py
@@
-133,6
+133,9
@@
class DMITAP(TAP):
dmi.we_i.eq(ds.ongoing("WRRD")),
]
dmi.we_i.eq(ds.ongoing("WRRD")),
]
+ def external_ports(self):
+ return [self.bus.tdo, self.bus.tdi, self.bus.tms, self.bus.tck]
+
if __name__ == '__main__':
dut = DMITAP(ir_width=4)
if __name__ == '__main__':
dut = DMITAP(ir_width=4)
diff --git
a/src/soc/debug/jtag.py
b/src/soc/debug/jtag.py
index 9e28e47b425401076e36e68a9ad01f15b848bc5b..67dadd7be625e697a21ad17695dc9ca6fab326f2 100644
(file)
--- a/
src/soc/debug/jtag.py
+++ b/
src/soc/debug/jtag.py
@@
-19,7
+19,8
@@
class JTAG(DMITAP):
# create and connect wishbone
self.wb = self.add_wishbone(ircodes=[5, 6, 7],
# create and connect wishbone
self.wb = self.add_wishbone(ircodes=[5, 6, 7],
- address_width=29, data_width=64)
+ address_width=29, data_width=64,
+ name="jtag_wb")
# create DMI2JTAG (goes through to dmi_sim())
self.dmi = self.add_dmi(ircodes=[8, 9, 10])
# create DMI2JTAG (goes through to dmi_sim())
self.dmi = self.add_dmi(ircodes=[8, 9, 10])
@@
-27,6
+28,11
@@
class JTAG(DMITAP):
def elaborate(self, platform):
return super().elaborate(platform)
def elaborate(self, platform):
return super().elaborate(platform)
+ def external_ports(self):
+ ports = super().external_ports()
+ ports += list(self.wb.fields.values())
+ return ports
+
if __name__ == '__main__':
dut = JTAG()
if __name__ == '__main__':
dut = JTAG()
diff --git
a/src/soc/simple/issuer.py
b/src/soc/simple/issuer.py
index f0b2b1bf30344b188198832f1da7b4157f142ec7..332dda805ebbbf3f9bbfe507853db47042a1699a 100644
(file)
--- a/
src/soc/simple/issuer.py
+++ b/
src/soc/simple/issuer.py
@@
-32,6
+32,7
@@
from soc.config.test.test_loadstore import TestMemPspec
from soc.config.ifetch import ConfigFetchUnit
from soc.decoder.power_enums import MicrOp
from soc.debug.dmi import CoreDebug, DMIInterface
from soc.config.ifetch import ConfigFetchUnit
from soc.decoder.power_enums import MicrOp
from soc.debug.dmi import CoreDebug, DMIInterface
+from soc.debug.jtag import JTAG
from soc.config.state import CoreState
from soc.interrupts.xics import XICS_ICP, XICS_ICS
from soc.bus.simple_gpio import SimpleGPIO
from soc.config.state import CoreState
from soc.interrupts.xics import XICS_ICP, XICS_ICS
from soc.bus.simple_gpio import SimpleGPIO
@@
-77,6
+78,11
@@
class TestIssuer(Elaboratable):
# DMI interface
self.dbg = CoreDebug()
# DMI interface
self.dbg = CoreDebug()
+ # JTAG interface
+ self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
+ if self.jtag_en:
+ self.jtag = JTAG()
+
# instruction go/monitor
self.pc_o = Signal(64, reset_less=True)
self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
# instruction go/monitor
self.pc_o = Signal(64, reset_less=True)
self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
@@
-109,6
+115,9
@@
class TestIssuer(Elaboratable):
m.submodules.core = core = DomainRenamer("coresync")(self.core)
m.submodules.imem = imem = self.imem
m.submodules.dbg = dbg = self.dbg
m.submodules.core = core = DomainRenamer("coresync")(self.core)
m.submodules.imem = imem = self.imem
m.submodules.dbg = dbg = self.dbg
+ if self.jtag_en:
+ m.submodules.jtag = jtag = self.jtag
+ comb += dbg.dmi.connect_to(jtag.dmi)
cur_state = self.cur_state
cur_state = self.cur_state
@@
-400,7
+409,13
@@
class TestIssuer(Elaboratable):
ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
ClockSignal(), ResetSignal(),
]
ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
ClockSignal(), ResetSignal(),
]
- ports += list(self.dbg.dmi.ports())
+
+ if self.jtag_en:
+ ports += list(self.jtag.external_ports())
+ else:
+ # don't add DMI if JTAG is enabled
+ ports += list(self.dbg.dmi.ports())
+
ports += list(self.imem.ibus.fields.values())
ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
ports += list(self.imem.ibus.fields.values())
ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
diff --git
a/src/soc/simple/issuer_verilog.py
b/src/soc/simple/issuer_verilog.py
index 8cd713f8d1393ad85f4179e078e44f47c8d4a37f..820e5fd32ddfb3603efcd53b0639d1eb22080ff7 100644
(file)
--- a/
src/soc/simple/issuer_verilog.py
+++ b/
src/soc/simple/issuer_verilog.py
@@
-29,6
+29,7
@@
if __name__ == '__main__':
#wb_data_wid=32,
xics=True,
gpio=False, # for test purposes
#wb_data_wid=32,
xics=True,
gpio=False, # for test purposes
+ debug="jtag", # set to jtag or dmi
units=units)
dut = TestIssuer(pspec)
units=units)
dut = TestIssuer(pspec)