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sync on pc writing when changed
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 13 Aug 2020 20:33:25 +0000
(21:33 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 13 Aug 2020 21:23:20 +0000
(22:23 +0100)
src/soc/simple/issuer.py
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diff --git
a/src/soc/simple/issuer.py
b/src/soc/simple/issuer.py
index d0a837a14e730f42cb10aaadc313342f55f50b0f..42bb5977608de57079c2219e36d59c02a056de4d 100644
(file)
--- a/
src/soc/simple/issuer.py
+++ b/
src/soc/simple/issuer.py
@@
-131,6
+131,13
@@
class TestIssuer(Elaboratable):
comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
comb += pc.eq(self.state_r_pc.data_o)
comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
comb += pc.eq(self.state_r_pc.data_o)
+ # don't write pc every cycle
+ sync += self.state_w_pc.wen.eq(0)
+ sync += self.state_w_pc.data_i.eq(0)
+
+ # don't read msr every cycle
+ sync += self.state_r_msr.ren.eq(0)
+
# connect up debug signals
# TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
comb += core.core_stopped_i.eq(dbg.core_stop_o)
# connect up debug signals
# TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
comb += core.core_stopped_i.eq(dbg.core_stop_o)
@@
-149,9
+156,6
@@
class TestIssuer(Elaboratable):
insn_type = core.pdecode2.e.do.insn_type
insn_state = core.pdecode2.state
insn_type = core.pdecode2.e.do.insn_type
insn_state = core.pdecode2.state
- # don't read msr every cycle
- sync += self.state_r_msr.ren.eq(0)
-
# actually use a nmigen FSM for the first time (w00t)
# this FSM is perhaps unusual in that it detects conditions
# then "holds" information, combinatorially, for the core
# actually use a nmigen FSM for the first time (w00t)
# this FSM is perhaps unusual in that it detects conditions
# then "holds" information, combinatorially, for the core
@@
-215,8
+219,8
@@
class TestIssuer(Elaboratable):
# this just blithely overwrites whatever pipeline
# updated the PC
with m.If(~pc_changed):
# this just blithely overwrites whatever pipeline
# updated the PC
with m.If(~pc_changed):
-
comb
+= self.state_w_pc.wen.eq(1<<StateRegs.PC)
-
comb
+= self.state_w_pc.data_i.eq(nia)
+
sync
+= self.state_w_pc.wen.eq(1<<StateRegs.PC)
+
sync
+= self.state_w_pc.data_i.eq(nia)
m.next = "IDLE" # back to idle
# this bit doesn't have to be in the FSM: connect up to read
m.next = "IDLE" # back to idle
# this bit doesn't have to be in the FSM: connect up to read