projects
/
soc.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
d46686e
)
add comments on MSR read
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 5 Sep 2020 20:43:04 +0000
(21:43 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 5 Sep 2020 20:43:04 +0000
(21:43 +0100)
src/soc/simple/issuer.py
patch
|
blob
|
history
diff --git
a/src/soc/simple/issuer.py
b/src/soc/simple/issuer.py
index 58c9769b7b59f296556789e983c8ded8192e1e77..ff525e9824b0079be601b86e5d2d6e2a430aa0fc 100644
(file)
--- a/
src/soc/simple/issuer.py
+++ b/
src/soc/simple/issuer.py
@@
-226,7
+226,7
@@
class TestIssuer(Elaboratable):
comb += self.imem.f_valid_i.eq(1)
sync += cur_state.pc.eq(pc)
comb += self.imem.f_valid_i.eq(1)
sync += cur_state.pc.eq(pc)
- # initiate read of MSR
+ # initiate read of MSR
. arrives one clock later
comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
sync += msr_read.eq(0)
comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
sync += msr_read.eq(0)
@@
-237,9
+237,9
@@
class TestIssuer(Elaboratable):
# dummy pause to find out why simulation is not keeping up
with m.State("INSN_READ"):
# dummy pause to find out why simulation is not keeping up
with m.State("INSN_READ"):
- # one cycle later, msr read arrives
+ # one cycle later, msr read arrives
. valid only once.
with m.If(~msr_read):
with m.If(~msr_read):
- sync += msr_read.eq(1)
+ sync += msr_read.eq(1)
# yeah don't read it again
sync += cur_state.msr.eq(self.state_r_msr.data_o)
with m.If(self.imem.f_busy_o): # zzz...
# busy: stay in wait-read
sync += cur_state.msr.eq(self.state_r_msr.data_o)
with m.If(self.imem.f_busy_o): # zzz...
# busy: stay in wait-read