move GPIO IRQ to 15 to match microwatt modifications

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index b0760b811237ae4490e0807cdf9efc81637e9ff9..311e8cfac2b93464727c71e4b64bd4ff92be5153 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -51,7 +51,7 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()

-        self.interrupt    = Signal(16)
+        self.interrupt    = Signal(4)

 
         if variant == "standard32":
             self.data_width           = 32
 
         if variant == "standard32":
             self.data_width           = 32

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index d2b573bb3b61d77bfce809ab2d1a8b1644d7f686..58c9769b7b59f296556789e983c8ded8192e1e77 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -121,9 +121,9 @@ class TestIssuer(Elaboratable):
         if self.gpio:
             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 
         if self.gpio:
             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 

-        # connect one GPIO output to ICS bit 5 (like in microwatt soc.vhdl)
+        # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)

         if self.gpio and self.xics:
         if self.gpio and self.xics:

-            comb += self.int_level_i[5].eq(simple_gpio.gpio_o[0])
+            comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])

 
         # instruction decoder
         pdecode = create_pdecode()
 
         # instruction decoder
         pdecode = create_pdecode()