restrict external port list further in test_issuer

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 854a5e66f7133da20b397a080b361dc63ba6853a..a273fd1656d2c393116d5c4485ac0c2c7b7591ca 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -221,8 +221,8 @@ class TestIssuer(Elaboratable):
                                     self.busy_o,
                                     self.halted_o,
                                     ] + \
-                self.imem.ports() + \
-                self.core.l0.cmpi.lsmem.lsi.ports()
+                list(self.imem.ibus.fields.values()) + \
+                list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
 
 
     def ports(self):