git.libre-soc.org Git - soc.git/history - src/soc/simple/issuer.py

[soc.git] / src / soc / simple / issuer.py

2020-07-31	Luke Kenneth Casso...	restrict external port list further in test_issuer	blob \| commitdiff \| raw
2020-07-30	Luke Kenneth Casso...	core_start/stop/endian were inverted (output)	blob \| commitdiff \| raw \| diff to current
2020-07-30	Luke Kenneth Casso...	ha! have to explicitly specify the ports when writing...	blob \| commitdiff \| raw \| diff to current
2020-07-29	Luke Kenneth Casso...	bit of a big change: add prefixes "cu_" to all CompUnit...	blob \| commitdiff \| raw \| diff to current
2020-07-23	Luke Kenneth Casso...	allow imem to be 64/32 bit wide	blob \| commitdiff \| raw \| diff to current
2020-07-22	Luke Kenneth Casso...	missing ports from issuer, when doing verilog	blob \| commitdiff \| raw \| diff to current
2020-07-22	Luke Kenneth Casso...	reduce number of FastRegs read ports	blob \| commitdiff \| raw \| diff to current
2020-07-21	Luke Kenneth Casso...	add PC (CIA) to PowerDecode2 "state" for passing into...	blob \| commitdiff \| raw \| diff to current
2020-07-19	Luke Kenneth Casso...	expose core_stop_i to outside as well	blob \| commitdiff \| raw \| diff to current
2020-07-19	Luke Kenneth Casso...	set go_insn_i to non-resetless	blob \| commitdiff \| raw \| diff to current
2020-07-19	Luke Kenneth Casso...	update to expose signals at top-level of issuer	blob \| commitdiff \| raw \| diff to current
2020-07-18	Luke Kenneth Casso...	add option to generate verilog	blob \| commitdiff \| raw \| diff to current
2020-07-14	Luke Kenneth Casso...	add MSR reading to issue FSM	blob \| commitdiff \| raw \| diff to current
2020-07-12	Luke Kenneth Casso...	rename InternalOp to MicrOp	blob \| commitdiff \| raw \| diff to current
2020-07-12	Luke Kenneth Casso...	exit FSM when termination detected	blob \| commitdiff \| raw \| diff to current
2020-07-08	Jacob Lifshay	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-07-07	Luke Kenneth Casso...	sort-of got binary execution test working	blob \| commitdiff \| raw \| diff to current
2020-07-07	Luke Kenneth Casso...	code-shuffle on testing to prepare loading large files...	blob \| commitdiff \| raw \| diff to current
2020-07-07	Luke Kenneth Casso...	add core start/stop capability, and OP_ATTN support	blob \| commitdiff \| raw \| diff to current
2020-07-06	Luke Kenneth Casso...	add mul unit to test_issuer	blob \| commitdiff \| raw \| diff to current
2020-07-05	Luke Kenneth Casso...	add slow spr regfile regspec support	blob \| commitdiff \| raw \| diff to current
2020-07-02	Luke Kenneth Casso...	allow flexible selection of the types of ALUs	blob \| commitdiff \| raw \| diff to current
2020-07-02	Luke Kenneth Casso...	add bare wishbone option to TestIssuer, sort out ports	blob \| commitdiff \| raw \| diff to current
2020-07-02	Luke Kenneth Casso...	use single-arg pspec for TestIssuer and Core	blob \| commitdiff \| raw \| diff to current
2020-07-01	Luke Kenneth Casso...	add name "test_issuer" to ilang conversion	blob \| commitdiff \| raw \| diff to current
2020-06-28	Luke Kenneth Casso...	read from instruction memory using FetchUnitInterface	blob \| commitdiff \| raw \| diff to current
2020-06-28	Luke Kenneth Casso...	expand instruction bus width to 64 bit, start on a...	blob \| commitdiff \| raw \| diff to current
2020-06-27	Luke Kenneth Casso...	make PortInterface modules consistent with same API	blob \| commitdiff \| raw \| diff to current
2020-06-18	Jacob Lifshay	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-06-18	Luke Kenneth Casso...	got loop example operational by noting when PC fastreg...	blob \| commitdiff \| raw \| diff to current
2020-06-18	Luke Kenneth Casso...	slightly hacky way to keep an eye on the PC	blob \| commitdiff \| raw \| diff to current
2020-06-17	Luke Kenneth Casso...	split out TestIssuer into separate module	blob \| commitdiff \| raw \| diff to current

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