src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import Elaboratable, Module, Signal
  19 from nmigen.cli import rtlil
  20
  21
  22 from soc.decoder.decode2execute1 import Data
  23 from soc.experiment.testmem import TestMemory # test only for instructions
  24 from soc.regfile.regfiles import FastRegs
  25 from soc.simple.core import NonProductionCore
  26
  27
  28 class TestIssuer(Elaboratable):
  29     """TestIssuer - reads instructions from TestMemory and issues them
  30
  31     efficiency and speed is not the main goal here: functional correctness is.
  32     """
  33     def __init__(self, addrwid=6, idepth=6, ifacetype='testpi'):
  34         # main instruction core
  35         self.core = core = NonProductionCore(addrwid, ifacetype=ifacetype)
  36
  37         # Test Instruction memory
  38         self.imemwid = 64
  39         self.imem = TestMemory(self.imemwid, idepth)
  40         self.i_rd = self.imem.rdport
  41         # one-row cache of instruction read
  42         self.iline = Signal(64) # one instruction line
  43         self.iprev_adr = Signal(64) # previous address: if different, do read
  44
  45         # instruction go/monitor
  46         self.go_insn_i = Signal(reset_less=True)
  47         self.pc_o = Signal(64, reset_less=True)
  48         self.pc_i = Data(64, "pc") # set "ok" to indicate "please change me"
  49         self.busy_o = core.busy_o
  50         self.memerr_o = Signal(reset_less=True)
  51
  52         # FAST regfile read /write ports
  53         self.fast_rd1 = self.core.regs.rf['fast'].r_ports['d_rd1']
  54         self.fast_wr1 = self.core.regs.rf['fast'].w_ports['d_wr1']
  55         # hack method of keeping an eye on whether branch/trap set the PC
  56         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  57         self.fast_nia.wen.name = 'fast_nia_wen'
  58
  59     def elaborate(self, platform):
  60         m = Module()
  61         comb, sync = m.d.comb, m.d.sync
  62
  63         m.submodules.core = core = self.core
  64         m.submodules.imem = imem = self.imem
  65
  66         # temporary hack: says "go" immediately for both address gen and ST
  67         l0 = core.l0
  68         ldst = core.fus.fus['ldst0']
  69         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
  70         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
  71
  72         # PC and instruction from I-Memory
  73         current_insn = Signal(32) # current fetched instruction (note sync)
  74         current_pc = Signal(64) # current PC (note it is reset/sync)
  75         pc_changed = Signal() # note write to PC
  76         comb += self.pc_o.eq(current_pc)
  77         ilatch = Signal(32)
  78
  79         # next instruction (+4 on current)
  80         nia = Signal(64, reset_less=True)
  81         comb += nia.eq(current_pc + 4)
  82
  83         # temporaries
  84         core_busy_o = core.busy_o         # core is busy
  85         core_ivalid_i = core.ivalid_i     # instruction is valid
  86         core_issue_i = core.issue_i       # instruction is issued
  87         core_be_i = core.bigendian_i      # bigendian mode
  88         core_opcode_i = core.raw_opcode_i # raw opcode
  89
  90         # actually use a nmigen FSM for the first time (w00t)
  91         with m.FSM() as fsm:
  92
  93             # waiting (zzz)
  94             with m.State("IDLE"):
  95                 sync += pc_changed.eq(0)
  96                 with m.If(self.go_insn_i):
  97                     # instruction allowed to go: start by reading the PC
  98                     pc = Signal(64, reset_less=True)
  99                     with m.If(self.pc_i.ok):
 100                         # incoming override (start from pc_i)
 101                         comb += pc.eq(self.pc_i.data)
 102                     with m.Else():
 103                         # otherwise read FastRegs regfile for PC
 104                         comb += self.fast_rd1.ren.eq(1<<FastRegs.PC)
 105                         comb += pc.eq(self.fast_rd1.data_o)
 106                     # capture the PC and also drop it into Insn Memory
 107                     # we have joined a pair of combinatorial memory
 108                     # lookups together.  this is Generally Bad.
 109                     comb += self.i_rd.addr.eq(pc[3:]) # ignore last 3 bits
 110                     sync += current_pc.eq(pc)
 111                     m.next = "INSN_READ" # move to "issue" phase
 112
 113             # got the instruction: start issue
 114             with m.State("INSN_READ"):
 115                 insn = self.i_rd.data.word_select(current_pc[2], 32) #
 116                 comb += current_insn.eq(insn)
 117                 comb += core_ivalid_i.eq(1) # say instruction is valid
 118                 comb += core_issue_i.eq(1)  # and issued (ivalid_i redundant)
 119                 comb += core_be_i.eq(0)     # little-endian mode
 120                 comb += core_opcode_i.eq(current_insn) # actual opcode
 121                 sync += ilatch.eq(current_insn)
 122                 m.next = "INSN_ACTIVE" # move to "wait for completion" phase
 123
 124             # instruction started: must wait till it finishes
 125             with m.State("INSN_ACTIVE"):
 126                 comb += core_ivalid_i.eq(1) # say instruction is valid
 127                 comb += core_opcode_i.eq(ilatch) # actual opcode
 128                 #sync += core_issue_i.eq(0) # issue raises for only one cycle
 129                 with m.If(self.fast_nia.wen):
 130                     sync += pc_changed.eq(1)
 131                 with m.If(~core_busy_o): # instruction done!
 132                     #sync += core_ivalid_i.eq(0) # say instruction is invalid
 133                     #sync += core_opcode_i.eq(0) # clear out (no good reason)
 134                     # ok here we are not reading the branch unit.  TODO
 135                     # this just blithely overwrites whatever pipeline updated
 136                     # the PC
 137                     with m.If(~pc_changed):
 138                         comb += self.fast_wr1.wen.eq(1<<FastRegs.PC)
 139                         comb += self.fast_wr1.data_i.eq(nia)
 140                     m.next = "IDLE" # back to idle
 141
 142         return m
 143
 144     def __iter__(self):
 145         yield from self.pc_i.ports()
 146         yield self.pc_o
 147         yield self.go_insn_i
 148         yield self.memerr_o
 149         yield from self.core.ports()
 150         yield from self.imem.ports()
 151
 152     def ports(self):
 153         return list(self)
 154
 155
 156 if __name__ == '__main__':
 157     dut = TestIssuer()
 158     vl = rtlil.convert(dut, ports=dut.ports())
 159     with open("test_issuer.il", "w") as f:
 160         f.write(vl)
 161