restrict external port list further in test_issuer

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 10f455866a4f7a51517a1a2ee80536b9dd9a5854..a273fd1656d2c393116d5c4485ac0c2c7b7591ca 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -56,9 +56,9 @@ class TestIssuer(Elaboratable):
         self.memerr_o = Signal(reset_less=True)
 
         # FAST regfile read /write ports for PC and MSR
-        self.fast_r_pc = self.core.regs.rf['fast'].r_ports['d_rd1'] # PC rd
+        self.fast_r_pc = self.core.regs.rf['fast'].r_ports['cia'] # PC rd
         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
-        self.fast_r_msr = self.core.regs.rf['fast'].r_ports['d_rd2'] # MSR rd
+        self.fast_r_msr = self.core.regs.rf['fast'].r_ports['msr'] # MSR rd
 
         # hack method of keeping an eye on whether branch/trap set the PC
         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
@@ -74,15 +74,15 @@ class TestIssuer(Elaboratable):
         # busy/halted signals from core
         comb += self.busy_o.eq(core.busy_o)
         comb += self.halted_o.eq(core.core_terminated_o)
-        comb += self.core_start_i.eq(core.core_start_i)
-        comb += self.core_stop_i.eq(core.core_stop_i)
-        comb += self.core_bigendian_i.eq(core.bigendian_i)
+        comb += core.core_start_i.eq(self.core_start_i)
+        comb += core.core_stop_i.eq(self.core_stop_i)
+        comb += core.bigendian_i.eq(self.core_bigendian_i)
 
         # temporary hack: says "go" immediately for both address gen and ST
         l0 = core.l0
         ldst = core.fus.fus['ldst0']
-        m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
-        m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
+        m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
+        m.d.comb += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
 
         # PC and instruction from I-Memory
         current_insn = Signal(32) # current fetched instruction (note sync)
@@ -150,7 +150,11 @@ class TestIssuer(Elaboratable):
                         comb += self.imem.f_valid_i.eq(1)
                     with m.Else():
                         # not busy: instruction fetched
-                        insn = self.imem.f_instr_o.word_select(cur_pc[2], 32)
+                        f_instr_o = self.imem.f_instr_o
+                        if f_instr_o.width == 32:
+                            insn = f_instr_o
+                        else:
+                            insn = f_instr_o.word_select(cur_pc[2], 32)
                         comb += current_insn.eq(insn)
                         comb += core_ivalid_i.eq(1) # instruction is valid
                         comb += core_issue_i.eq(1)  # and issued 
@@ -198,6 +202,28 @@ class TestIssuer(Elaboratable):
         yield self.memerr_o
         yield from self.core.ports()
         yield from self.imem.ports()
+        yield self.core_start_i
+        yield self.core_stop_i
+        yield self.core_bigendian_i
+        yield self.busy_o
+        yield self.halted_o
+
+    def ports(self):
+        return list(self)
+
+    def external_ports(self):
+        return self.pc_i.ports() + [self.pc_o,
+                                    self.go_insn_i,
+                                    self.memerr_o,
+                                    self.core_start_i,
+                                    self.core_stop_i,
+                                    self.core_bigendian_i,
+                                    self.busy_o,
+                                    self.halted_o,
+                                    ] + \
+                list(self.imem.ibus.fields.values()) + \
+                list(self.core.l0.cmpi.lsmem.lsi.dbus.fields.values())
+
 
     def ports(self):
         return list(self)
@@ -218,6 +244,6 @@ if __name__ == '__main__':
     vl = main(dut, ports=dut.ports(), name="test_issuer")
 
     if len(sys.argv) == 1:
-        vl = rtlil.convert(dut, ports=dut.ports(), name="test_issuer")
+        vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
         with open("test_issuer.il", "w") as f:
             f.write(vl)