update submodule

diff --git a/libreriscv b/libreriscv
index 30348c765a545765ebe16121738730d17174f955..a89e605aae22b1f7e26ddcb9577a8271d94d009e 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 30348c765a545765ebe16121738730d17174f955
+Subproject commit a89e605aae22b1f7e26ddcb9577a8271d94d009e

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 46e97d6964aaa0a7fb5e91964036126cc336b441..32bd638ea45244d10f2c26fa061c14a8f4273a04 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -2,6 +2,14 @@
 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 # Copyright (C) 2020, Michael Nolan
 
+"""Enums used in OpenPOWER ISA decoding
+
+Note: for SV, from v3.1B p12:
+
+    The designated SPR sandbox consists of non-privileged SPRs 704-719 and
+    privileged SPRs 720-735.
+"""
+
 from enum import Enum, unique
 import csv
 import os