intel/assembler: Add labels support

Use labels instead of numeric JIP/UIP offsets.
Works for gen6+.

v2:
 - Change asm tests to use labels on gen6+
 - Remove usage of relative offsets on gen6+
 - Consider brw_jump_scale when setting relative offset
 - Return error if there is a JIP/UIP label without matching target
 - Fix matching of label tokens

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245>

diff --git a/src/intel/tools/i965_asm.c b/src/intel/tools/i965_asm.c
index 1e6e0904b50b8642c8945157a54b4c02e0bb131b..2be74e375d46647a0ddfac2c3bb32b5ede50b659 100644 (file)
--- a/src/intel/tools/i965_asm.c
+++ b/src/intel/tools/i965_asm.c
@@ -38,6 +38,9 @@ static enum opt_output_type output_type = OPT_OUTPUT_BIN;
 char *input_filename = NULL;
 int errors;
 
+struct list_head instr_labels;
+struct list_head target_labels;
+
 static void
 print_help(const char *progname, FILE *file)
 {
@@ -119,6 +122,90 @@ i965_disasm_init(uint16_t pci_id)
    return devinfo;
 }
 
+static bool
+i965_postprocess_labels()
+{
+   if (p->devinfo->gen < 6) {
+      return true;
+   }
+
+   void *store = p->store;
+
+   struct target_label *tlabel;
+   struct instr_label *ilabel, *s;
+
+   const unsigned to_bytes_scale = brw_jump_scale(p->devinfo);
+
+   LIST_FOR_EACH_ENTRY(tlabel, &target_labels, link) {
+      LIST_FOR_EACH_ENTRY_SAFE(ilabel, s, &instr_labels, link) {
+         if (!strcmp(tlabel->name, ilabel->name)) {
+            brw_inst *inst = store + ilabel->offset;
+
+            int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(brw_inst);
+            relative_offset *= to_bytes_scale;
+
+            unsigned opcode = brw_inst_opcode(p->devinfo, inst);
+
+            if (ilabel->type == INSTR_LABEL_JIP) {
+               switch (opcode) {
+               case BRW_OPCODE_IF:
+               case BRW_OPCODE_ELSE:
+               case BRW_OPCODE_ENDIF:
+               case BRW_OPCODE_WHILE:
+                  if (p->devinfo->gen >= 7) {
+                     brw_inst_set_jip(p->devinfo, inst, relative_offset);
+                  } else if (p->devinfo->gen == 6) {
+                     brw_inst_set_gen6_jump_count(p->devinfo, inst, relative_offset);
+                  }
+                  break;
+               case BRW_OPCODE_BREAK:
+               case BRW_OPCODE_HALT:
+               case BRW_OPCODE_CONTINUE:
+                  brw_inst_set_jip(p->devinfo, inst, relative_offset);
+                  break;
+               default:
+                  fprintf(stderr, "Unknown opcode %d with JIP label\n", opcode);
+                  return false;
+               }
+            } else {
+               switch (opcode) {
+               case BRW_OPCODE_IF:
+               case BRW_OPCODE_ELSE:
+                  if (p->devinfo->gen > 7) {
+                     brw_inst_set_uip(p->devinfo, inst, relative_offset);
+                  } else if (p->devinfo->gen == 7) {
+                     brw_inst_set_uip(p->devinfo, inst, relative_offset);
+                  } else if (p->devinfo->gen == 6) {
+                     // Nothing
+                  }
+                  break;
+               case BRW_OPCODE_WHILE:
+               case BRW_OPCODE_ENDIF:
+                  fprintf(stderr, "WHILE/ENDIF cannot have UIP offset\n");
+                  return false;
+               case BRW_OPCODE_BREAK:
+               case BRW_OPCODE_CONTINUE:
+               case BRW_OPCODE_HALT:
+                  brw_inst_set_uip(p->devinfo, inst, relative_offset);
+                  break;
+               default:
+                  fprintf(stderr, "Unknown opcode %d with UIP label\n", opcode);
+                  return false;
+               }
+            }
+
+            list_del(&ilabel->link);
+         }
+      }
+   }
+
+   LIST_FOR_EACH_ENTRY(ilabel, &instr_labels, link) {
+      fprintf(stderr, "Unknown label '%s'\n", ilabel->name);
+   }
+
+   return list_is_empty(&instr_labels);
+}
+
 int main(int argc, char **argv)
 {
    char *output_file = NULL;
@@ -132,6 +219,8 @@ int main(int argc, char **argv)
    struct disasm_info *disasm_info;
    struct gen_device_info *devinfo = NULL;
    int result = EXIT_FAILURE;
+   list_inithead(&instr_labels);
+   list_inithead(&target_labels);
 
    const struct option i965_asm_opts[] = {
       { "help",          no_argument,       (int *) &help,      true },
@@ -230,6 +319,9 @@ int main(int argc, char **argv)
    if (err || errors)
       goto end;
 
+   if (!i965_postprocess_labels())
+      goto end;
+
    store = p->store;
 
    disasm_info = disasm_initialize(p->devinfo, NULL);

diff --git a/src/intel/tools/i965_asm.h b/src/intel/tools/i965_asm.h
index dd29208198fecb593dbdd0696557e28a3880e0d2..a7e4e86b36d96b54b88b65da287b45edcf0863bb 100644 (file)
--- a/src/intel/tools/i965_asm.h
+++ b/src/intel/tools/i965_asm.h
@@ -35,6 +35,7 @@
 #include "compiler/brw_inst.h"
 #include "compiler/brw_eu.h"
 #include "dev/gen_device_info.h"
+#include "util/list.h"
 
 /* glibc < 2.27 defines OVERFLOW in /usr/include/math.h. */
 #undef OVERFLOW
@@ -48,6 +49,9 @@ extern struct brw_codegen *p;
 extern int errors;
 extern char *input_filename;
 
+extern struct list_head instr_labels;
+extern struct list_head target_labels;
+
 struct condition {
    unsigned cond_modifier:4;
    unsigned flag_reg_nr:1;
@@ -77,4 +81,24 @@ struct options {
    unsigned is_compr:1;
 };
 
+enum instr_label_type {
+   INSTR_LABEL_JIP,
+   INSTR_LABEL_UIP,
+};
+
+struct instr_label {
+   struct list_head link;
+
+   char *name;
+   int offset;
+   enum instr_label_type type;
+};
+
+struct target_label {
+   struct list_head link;
+
+   char *name;
+   int offset;
+};
+
 #endif /* __I965_ASM_H__ */

diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y
index 2b657688e25bc6a81fc2720f6552051df43a367b..e5fb2282703052023c27735c768da5b20c23ce9b 100644 (file)
--- a/src/intel/tools/i965_gram.y
+++ b/src/intel/tools/i965_gram.y
@@ -310,6 +310,22 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
        }
 }
 
+static void
+add_label(struct brw_codegen *p, const char* label_name, enum instr_label_type type)
+{
+       if (!label_name) {
+               return;
+       }
+
+       struct instr_label *label = rzalloc(p->mem_ctx, struct instr_label);
+
+       label->name = ralloc_strdup(p->mem_ctx, label_name);
+       label->offset = p->next_insn_offset;
+       label->type = type;
+
+       list_addtail(&label->link, &instr_labels);
+}
+
 %}
 
 %locations
@@ -317,6 +333,7 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
 %start ROOT
 
 %union {
+       char *string;
        double number;
        int integer;
        unsigned long long int llint;
@@ -350,6 +367,10 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
 %token <integer> TYPE_DF TYPE_NF
 %token <integer> TYPE_VF
 
+/* label */
+%token <string> JUMP_LABEL
+%token <string> JUMP_LABEL_TARGET
+
 /* opcodes */
 %token <integer> ADD ADD3 ADDC AND ASR AVG
 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
@@ -502,6 +523,9 @@ i965_asm_set_dst_nr(struct brw_codegen *p,
 
 %type <integer> negate abs chansel math_function sharedfunction
 
+%type <string> jumplabeltarget
+%type <string> jumplabel
+
 %code {
 
 static void
@@ -608,6 +632,8 @@ instrseq:
        | instrseq relocatableinstruction SEMICOLON
        | instruction SEMICOLON
        | relocatableinstruction SEMICOLON
+       | instrseq jumplabeltarget
+       | jumplabeltarget
        ;
 
 /* Instruction Group */
@@ -1072,24 +1098,16 @@ jumpinstruction:
 
 /* branch instruction */
 branchinstruction:
-       predicate ENDIF execsize relativelocation instoptions
+       predicate ENDIF execsize JUMP_LABEL instoptions
        {
+               add_label(p, $4, INSTR_LABEL_JIP);
+
                brw_next_insn(p, $2);
                i965_asm_set_instruction_options(p, $5);
                brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 
-               if (p->devinfo->gen < 6) {
-                       brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
-                                    BRW_REGISTER_TYPE_D));
-                       brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
-                                    BRW_REGISTER_TYPE_D));
-                       brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
-                       brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
-                                                   $4);
-               } else if (p->devinfo->gen == 6) {
+               if (p->devinfo->gen == 6) {
                        brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
-                       brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
-                                                    $4);
                        brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
                        brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
@@ -1100,34 +1118,41 @@ branchinstruction:
                        brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
                        brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
                } else {
-                       brw_set_src0(p, brw_last_inst, brw_imm_d($4));
+                       brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
                }
 
-               if (p->devinfo->gen < 6)
-                       brw_inst_set_thread_control(p->devinfo, brw_last_inst,
-                                                   BRW_THREAD_SWITCH);
                brw_pop_insn_state(p);
        }
-       | ELSE execsize relativelocation rellocation instoptions
+       | predicate ENDIF execsize relativelocation instoptions
+       {
+               brw_next_insn(p, $2);
+               i965_asm_set_instruction_options(p, $5);
+               brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+               brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
+                                       BRW_REGISTER_TYPE_D));
+               brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
+                                       BRW_REGISTER_TYPE_D));
+               brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+               brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
+
+               brw_inst_set_thread_control(p->devinfo, brw_last_inst,
+                                               BRW_THREAD_SWITCH);
+
+               brw_pop_insn_state(p);
+       }
+       | ELSE execsize JUMP_LABEL jumplabel instoptions
        {
+               add_label(p, $3, INSTR_LABEL_JIP);
+               add_label(p, $4, INSTR_LABEL_UIP);
+
                brw_next_insn(p, $1);
                i965_asm_set_instruction_options(p, $5);
                brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 
-               if (p->devinfo->gen < 6) {
-                       brw_set_dest(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src0(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
-                       brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
-                                                    $3);
-                       brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
-                                                   $4);
-               } else if (p->devinfo->gen == 6) {
+               if (p->devinfo->gen == 6) {
                        brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
-                       brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
-                                                    $3);
                        brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
                        brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
@@ -1137,39 +1162,41 @@ branchinstruction:
                                     BRW_REGISTER_TYPE_D));
                        brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
-                       brw_set_src1(p, brw_last_inst, brw_imm_w($3));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
-                       brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
+                       brw_set_src1(p, brw_last_inst, brw_imm_w(0));
                } else {
                        brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
-                       brw_set_src0(p, brw_last_inst, brw_imm_d($3));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
-                       brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
+                       if (p->devinfo->gen < 12)
+                               brw_set_src0(p, brw_last_inst, brw_imm_d(0));
                }
+       }
+       | ELSE execsize relativelocation rellocation instoptions
+       {
+               brw_next_insn(p, $1);
+               i965_asm_set_instruction_options(p, $5);
+               brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
 
-               if (!p->single_program_flow && p->devinfo->gen < 6)
+               brw_set_dest(p, brw_last_inst, brw_ip_reg());
+               brw_set_src0(p, brw_last_inst, brw_ip_reg());
+               brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+               brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $3);
+               brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $4);
+
+               if (!p->single_program_flow)
                        brw_inst_set_thread_control(p->devinfo, brw_last_inst,
                                                    BRW_THREAD_SWITCH);
        }
-       | predicate IF execsize relativelocation rellocation instoptions
+       | predicate IF execsize JUMP_LABEL jumplabel instoptions
        {
+               add_label(p, $4, INSTR_LABEL_JIP);
+               add_label(p, $5, INSTR_LABEL_UIP);
+
                brw_next_insn(p, $2);
                i965_asm_set_instruction_options(p, $6);
                brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 
-               if (p->devinfo->gen < 6) {
-                       brw_set_dest(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src0(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
-                       brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
-                                                    $4);
-                       brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
-                                                   $5);
-               } else if (p->devinfo->gen == 6) {
+               if (p->devinfo->gen == 6) {
                        brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
-                       brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
-                                                    $4);
                        brw_set_src0(p, brw_last_inst,
                                     vec1(retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D)));
@@ -1183,40 +1210,44 @@ branchinstruction:
                        brw_set_src0(p, brw_last_inst,
                                     vec1(retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D)));
-                       brw_set_src1(p, brw_last_inst, brw_imm_w($4));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
-                       brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
+                       brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
                } else {
                        brw_set_dest(p, brw_last_inst,
                                     vec1(retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D)));
-                       brw_set_src0(p, brw_last_inst, brw_imm_d($4));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
-                       brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
+                       if (p->devinfo->gen < 12)
+                               brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
                }
 
-               if (!p->single_program_flow && p->devinfo->gen < 6)
+               brw_pop_insn_state(p);
+       }
+       | predicate IF execsize relativelocation rellocation instoptions
+       {
+               brw_next_insn(p, $2);
+               i965_asm_set_instruction_options(p, $6);
+               brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+               brw_set_dest(p, brw_last_inst, brw_ip_reg());
+               brw_set_src0(p, brw_last_inst, brw_ip_reg());
+               brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+               brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+               brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
+
+               if (!p->single_program_flow)
                        brw_inst_set_thread_control(p->devinfo, brw_last_inst,
                                                    BRW_THREAD_SWITCH);
 
                brw_pop_insn_state(p);
        }
-       | predicate IFF execsize relativelocation instoptions
+       | predicate IFF execsize JUMP_LABEL instoptions
        {
+               add_label(p, $4, INSTR_LABEL_JIP);
+
                brw_next_insn(p, $2);
                i965_asm_set_instruction_options(p, $5);
                brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 
-               if (p->devinfo->gen < 6) {
-                       brw_set_dest(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src0(p, brw_last_inst, brw_ip_reg());
-                       brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
-                                                    $4);
-                       brw_set_src1(p, brw_last_inst, brw_imm_d($4));
-               } else if (p->devinfo->gen == 6) {
-                       brw_set_dest(p, brw_last_inst, brw_imm_w($4));
-                       brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
-                                                    $4);
+               if (p->devinfo->gen == 6) {
                        brw_set_src0(p, brw_last_inst,
                                     vec1(retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D)));
@@ -1230,17 +1261,29 @@ branchinstruction:
                        brw_set_src0(p, brw_last_inst,
                                     vec1(retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D)));
-                       brw_set_src1(p, brw_last_inst, brw_imm_w($4));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
+                       brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
                } else {
                        brw_set_dest(p, brw_last_inst,
                                     vec1(retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D)));
-                       brw_set_src0(p, brw_last_inst, brw_imm_d($4));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
+                       if (p->devinfo->gen < 12)
+                               brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
                }
 
-               if (!p->single_program_flow && p->devinfo->gen < 6)
+               brw_pop_insn_state(p);
+       }
+       | predicate IFF execsize relativelocation instoptions
+       {
+               brw_next_insn(p, $2);
+               i965_asm_set_instruction_options(p, $5);
+               brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+               brw_set_dest(p, brw_last_inst, brw_ip_reg());
+               brw_set_src0(p, brw_last_inst, brw_ip_reg());
+               brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+               brw_set_src1(p, brw_last_inst, brw_imm_d($4));
+
+               if (!p->single_program_flow)
                        brw_inst_set_thread_control(p->devinfo, brw_last_inst,
                                                    BRW_THREAD_SWITCH);
 
@@ -1250,8 +1293,11 @@ branchinstruction:
 
 /* break instruction */
 breakinstruction:
-       predicate BREAK execsize relativelocation relativelocation instoptions
+       predicate BREAK execsize JUMP_LABEL JUMP_LABEL instoptions
        {
+               add_label(p, $4, INSTR_LABEL_JIP);
+               add_label(p, $5, INSTR_LABEL_UIP);
+
                brw_next_insn(p, $2);
                i965_asm_set_instruction_options(p, $6);
                brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
@@ -1259,51 +1305,58 @@ breakinstruction:
                if (p->devinfo->gen >= 8) {
                        brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
-                       brw_set_src0(p, brw_last_inst, brw_imm_d($4));
-                       brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
-               } else if (p->devinfo->gen >= 6) {
+                       brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
+               } else {
                        brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
                        brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
                        brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
-                       brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
-               } else {
-                       brw_set_dest(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src0(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
-                       brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
-                                                    $4);
-                       brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
-                                                   $5);
                }
 
                brw_pop_insn_state(p);
        }
-       | predicate HALT execsize relativelocation relativelocation instoptions
+       | predicate BREAK execsize relativelocation relativelocation instoptions
+       {
+               brw_next_insn(p, $2);
+               i965_asm_set_instruction_options(p, $6);
+               brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+               brw_set_dest(p, brw_last_inst, brw_ip_reg());
+               brw_set_src0(p, brw_last_inst, brw_ip_reg());
+               brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+               brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+               brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
+
+               brw_pop_insn_state(p);
+       }
+       | predicate HALT execsize JUMP_LABEL JUMP_LABEL instoptions
        {
+               add_label(p, $4, INSTR_LABEL_JIP);
+               add_label(p, $5, INSTR_LABEL_UIP);
+
                brw_next_insn(p, $2);
                i965_asm_set_instruction_options(p, $6);
                brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
                brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
                             BRW_REGISTER_TYPE_D));
 
                if (p->devinfo->gen >= 8) {
-                       brw_set_src0(p, brw_last_inst, brw_imm_d($4));
-                       brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
+                       brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
                } else {
                        brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
                                     BRW_REGISTER_TYPE_D));
-                       brw_set_src1(p, brw_last_inst, brw_imm_d($5));
+                       brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
                }
 
-               brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
-               brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
                brw_pop_insn_state(p);
        }
-       | predicate CONT execsize relativelocation relativelocation instoptions
+       | predicate CONT execsize JUMP_LABEL JUMP_LABEL instoptions
        {
+               add_label(p, $4, INSTR_LABEL_JIP);
+               add_label(p, $5, INSTR_LABEL_UIP);
+
                brw_next_insn(p, $2);
                i965_asm_set_instruction_options(p, $6);
                brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
@@ -1311,72 +1364,78 @@ breakinstruction:
 
                if (p->devinfo->gen >= 8) {
                        brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
-                       brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
-                       brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
                } else {
                        brw_set_src0(p, brw_last_inst, brw_ip_reg());
                        brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
-                       if (p->devinfo->gen >= 6) {
-                               brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
-                               brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
-                       } else {
-                               brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
-                                                            $4);
-                               brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
-                                                           $5);
-                       }
                }
 
                brw_pop_insn_state(p);
        }
+       | predicate CONT execsize relativelocation relativelocation instoptions
+       {
+               brw_next_insn(p, $2);
+               i965_asm_set_instruction_options(p, $6);
+               brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+               brw_set_dest(p, brw_last_inst, brw_ip_reg());
+
+               brw_set_src0(p, brw_last_inst, brw_ip_reg());
+               brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+
+               brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+               brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, $5);
+
+               brw_pop_insn_state(p);
+       }
        ;
 
 /* loop instruction */
 loopinstruction:
-       predicate WHILE execsize relativelocation instoptions
+       predicate WHILE execsize JUMP_LABEL instoptions
        {
+               add_label(p, $4, INSTR_LABEL_JIP);
+
                brw_next_insn(p, $2);
                i965_asm_set_instruction_options(p, $5);
                brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
 
-               if (p->devinfo->gen >= 6) {
-                       if (p->devinfo->gen >= 8) {
-                               brw_set_dest(p, brw_last_inst,
-                                            retype(brw_null_reg(),
-                                            BRW_REGISTER_TYPE_D));
-                               brw_set_src0(p, brw_last_inst, brw_imm_d($4));
-                       } else if (p->devinfo->gen == 7) {
-                               brw_set_dest(p, brw_last_inst,
-                                            retype(brw_null_reg(),
-                                            BRW_REGISTER_TYPE_D));
-                               brw_set_src0(p, brw_last_inst,
-                                            retype(brw_null_reg(),
-                                            BRW_REGISTER_TYPE_D));
-                               brw_set_src1(p, brw_last_inst,
-                                            brw_imm_w(0x0));
-                               brw_inst_set_jip(p->devinfo, brw_last_inst,
-                                                $4);
-                       } else {
-                               brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
-                               brw_inst_set_gen6_jump_count(p->devinfo,
-                                                            brw_last_inst,
-                                                            $4);
-                               brw_set_src0(p, brw_last_inst,
-                                            retype(brw_null_reg(),
-                                            BRW_REGISTER_TYPE_D));
-                               brw_set_src1(p, brw_last_inst,
-                                            retype(brw_null_reg(),
-                                            BRW_REGISTER_TYPE_D));
-                       }
+               if (p->devinfo->gen >= 8) {
+                       brw_set_dest(p, brw_last_inst,
+                                               retype(brw_null_reg(),
+                                               BRW_REGISTER_TYPE_D));
+                       brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
+               } else if (p->devinfo->gen == 7) {
+                       brw_set_dest(p, brw_last_inst,
+                                               retype(brw_null_reg(),
+                                               BRW_REGISTER_TYPE_D));
+                       brw_set_src0(p, brw_last_inst,
+                                               retype(brw_null_reg(),
+                                               BRW_REGISTER_TYPE_D));
+                       brw_set_src1(p, brw_last_inst,
+                                               brw_imm_w(0x0));
                } else {
-                       brw_set_dest(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src0(p, brw_last_inst, brw_ip_reg());
-                       brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
-                       brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
-                                                    $4);
-                       brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
-                                                   0);
+                       brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
+                       brw_set_src0(p, brw_last_inst,
+                                               retype(brw_null_reg(),
+                                               BRW_REGISTER_TYPE_D));
+                       brw_set_src1(p, brw_last_inst,
+                                               retype(brw_null_reg(),
+                                               BRW_REGISTER_TYPE_D));
                }
+
+               brw_pop_insn_state(p);
+       }
+       | predicate WHILE execsize relativelocation instoptions
+       {
+               brw_next_insn(p, $2);
+               i965_asm_set_instruction_options(p, $5);
+               brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
+
+               brw_set_dest(p, brw_last_inst, brw_ip_reg());
+               brw_set_src0(p, brw_last_inst, brw_ip_reg());
+               brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
+               brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst, $4);
+               brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst, 0);
+
                brw_pop_insn_state(p);
        }
        | DO execsize instoptions
@@ -1419,6 +1478,23 @@ relativelocation:
        }
        ;
 
+jumplabel:
+       JUMP_LABEL      { $$ = $1; }
+       | %empty        { $$ = NULL; }
+       ;
+
+jumplabeltarget:
+       JUMP_LABEL_TARGET
+       {
+               struct target_label *label = rzalloc(p->mem_ctx, struct target_label);
+
+               label->name = ralloc_strdup(p->mem_ctx, $1);
+               label->offset = p->next_insn_offset;
+
+               list_addtail(&label->link, &target_labels);
+       }
+       ;
+
 /* Destination register */
 dst:
        dstoperand

diff --git a/src/intel/tools/i965_lex.l b/src/intel/tools/i965_lex.l
index 4e575a3253ffaa9b9e301c6a938d36f2251ce403..77986361123ac0b660773f6dd7c73f3edb950f3c 100644 (file)
--- a/src/intel/tools/i965_lex.l
+++ b/src/intel/tools/i965_lex.l
@@ -24,6 +24,7 @@ extern char *input_filename;
 %x CHANNEL
 %x REG
 %x DOTSEL
+%x LABEL
 %%
 
  /* eat up single line comment */
@@ -367,8 +368,8 @@ sr[0-9]+    { yylval.integer = atoi(yytext + 2); return STATEREG; }
  /* Eat up JIP and UIP token, their values will be parsed
   * in numeric section
   */
-"JIP: "                { }
-"UIP: "                { }
+"JIP: "                { BEGIN(LABEL); }
+"UIP: "                { BEGIN(LABEL); }
 "Jump: "               { }
 "Pop: "                { }
 [ \t]+                 { }
@@ -383,6 +384,21 @@ sr[0-9]+   { yylval.integer = atoi(yytext + 2); return STATEREG; }
                           return LONG;
                        }
 
+ /* jump label target */
+[a-zA-Z_][0-9a-zA-Z_]*":" {
+       yylval.string = ralloc_strdup(p->mem_ctx, yytext);
+       /* Stomp the trailing ':' */
+       yylval.string[yyleng - 1] = '\0';
+       return JUMP_LABEL_TARGET;
+}
+
+ /* jump label */
+<LABEL>[a-zA-Z_][0-9a-zA-Z_]* {
+       yylval.string = ralloc_strdup(p->mem_ctx, yytext);
+       BEGIN(INITIAL);
+       return JUMP_LABEL;
+}
+
 \n     { yycolumn = 1; }
 
 .      {

diff --git a/src/intel/tools/tests/gen6/break.asm b/src/intel/tools/tests/gen6/break.asm
index 4b8afa9d11c99422d068382e3abddf00a4f4b357..afb858641295cf7e97e9d6ad00110a90159b3e44 100644 (file)
--- a/src/intel/tools/tests/gen6/break.asm
+++ b/src/intel/tools/tests/gen6/break.asm
@@ -1,6 +1,9 @@
-break(8)        JIP: 2          UIP: 12                         { align16 1Q };
-break(8)        JIP: 2          UIP: 104                        { align1 1Q };
-break(16)       JIP: 2          UIP: 104                        { align1 1H };
-(+f0.0) break(8) JIP: 4         UIP: 12                         { align1 1Q };
-(+f0.0) break(16) JIP: 4        UIP: 12                         { align1 1H };
-(+f0.0.x) break(8) JIP: 122     UIP: 124                        { align16 1Q };
+break(8)        JIP: LABEL1    UIP: LABEL2                    { align16 1Q };
+LABEL1:
+break(8)        JIP: LABEL2    UIP: LABEL2                    { align1 1Q };
+break(16)       JIP: LABEL2    UIP: LABEL2                    { align1 1H };
+LABEL2:
+(+f0.0) break(8) JIP: LABEL3   UIP: LABEL3                    { align1 1Q };
+(+f0.0) break(16) JIP: LABEL3  UIP: LABEL3                    { align1 1H };
+(+f0.0.x) break(8) JIP: LABEL3 UIP: LABEL3                    { align16 1Q };
+LABEL3:

diff --git a/src/intel/tools/tests/gen6/break.expected b/src/intel/tools/tests/gen6/break.expected
index 9ab35eca7f181f2f388bf41d55fffff6f6329b3a..dcf4d4f721dfd232be4e1888f57796da8fd40c73 100644 (file)
--- a/src/intel/tools/tests/gen6/break.expected
+++ b/src/intel/tools/tests/gen6/break.expected
@@ -1,6 +1,6 @@
-28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0c 00
-28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 68 00
-28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 68 00
-28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0c 00
-28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0c 00
-28 01 62 00 84 1c 0f 20 04 00 6e 00 7a 00 7c 00
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 06 00
+28 00 60 00 84 1c 00 20 00 00 8d 00 04 00 04 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen6/cont.asm b/src/intel/tools/tests/gen6/cont.asm
index 7f7a9c4219699ad26667ae1ecc71775351975e5d..497a1155efc895f51540e75dbb0253e520c658aa 100644 (file)
--- a/src/intel/tools/tests/gen6/cont.asm
+++ b/src/intel/tools/tests/gen6/cont.asm
@@ -1,3 +1,6 @@
-cont(8)         JIP: 2          UIP: 8                          { align1 1Q };
-cont(16)        JIP: 2          UIP: 8                          { align1 1H };
-cont(8)         JIP: 2          UIP: 8                          { align16 1Q };
+cont(8)         JIP: LABEL0          UIP: LABEL2                { align1 1Q };
+LABEL0:
+cont(16)        JIP: LABEL1          UIP: LABEL2                { align1 1H };
+LABEL1:
+cont(8)         JIP: LABEL2          UIP: LABEL2                { align16 1Q };
+LABEL2:

diff --git a/src/intel/tools/tests/gen6/cont.expected b/src/intel/tools/tests/gen6/cont.expected
index a8376c2f2d577e0bf70e0d2ef050ab32adffded9..704ea3afd86be4ccb547346a1c64dd2347c8ed59 100644 (file)
--- a/src/intel/tools/tests/gen6/cont.expected
+++ b/src/intel/tools/tests/gen6/cont.expected
@@ -1,3 +1,3 @@
-29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00
-29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00
-29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00
+29 00 60 00 00 1c 00 34 00 14 60 00 02 00 06 00
+29 00 80 00 00 1c 00 34 00 14 60 00 02 00 04 00
+29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen6/else.asm b/src/intel/tools/tests/gen6/else.asm
index 71a09a3996d6819575a0ee2567464a921b3367c4..b3f404427ffb90b16fefc9b3f628f15a6fd175c6 100644 (file)
--- a/src/intel/tools/tests/gen6/else.asm
+++ b/src/intel/tools/tests/gen6/else.asm
@@ -1,3 +1,4 @@
-else(8)         JIP: 12                                         { align1 1Q };
-else(16)        JIP: 12                                         { align1 1H };
-else(8)         JIP: 18                                         { align16 1Q };
+else(8)         JIP: LABEL0                                    { align1 1Q };
+else(16)        JIP: LABEL0                                    { align1 1H };
+else(8)         JIP: LABEL0                                    { align16 1Q };
+LABEL0:

diff --git a/src/intel/tools/tests/gen6/else.expected b/src/intel/tools/tests/gen6/else.expected
index 9e1b70e0ac34534874332275dbb8ae4b968cedbb..05f52d5c6c4f06fef27273fcde664950dae3df75 100644 (file)
--- a/src/intel/tools/tests/gen6/else.expected
+++ b/src/intel/tools/tests/gen6/else.expected
@@ -1,3 +1,3 @@
-24 00 60 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00
-24 00 80 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00
-24 01 60 00 8f 10 12 00 04 00 6e 00 04 00 6e 00
+24 00 60 00 8f 10 06 00 00 00 8d 00 00 00 8d 00
+24 00 80 00 8f 10 04 00 00 00 8d 00 00 00 8d 00
+24 01 60 00 8f 10 02 00 04 00 6e 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen6/endif.asm b/src/intel/tools/tests/gen6/endif.asm
index b3a5066cb53d53f11bc591481becb89272d792e5..c60151653672d599feb9741f3b1ad7996535ec14 100644 (file)
--- a/src/intel/tools/tests/gen6/endif.asm
+++ b/src/intel/tools/tests/gen6/endif.asm
@@ -1,3 +1,6 @@
-endif(8)        JIP: 2                                          { align16 1Q };
-endif(8)        JIP: 2                                          { align1 1Q };
-endif(16)       JIP: 2                                          { align1 1H };
+endif(8)        JIP: LABEL1                                          { align16 1Q };
+LABEL1:
+endif(8)        JIP: LABEL2                                          { align1 1Q };
+LABEL2:
+endif(16)       JIP: LABEL3                                          { align1 1H };
+LABEL3:

diff --git a/src/intel/tools/tests/gen6/halt.asm b/src/intel/tools/tests/gen6/halt.asm
index 3674b30d6ba50c02318f9670b37f290f96952c6a..5f29e88c57cf7730dea705a7da83ea3ce8e7e344 100644 (file)
--- a/src/intel/tools/tests/gen6/halt.asm
+++ b/src/intel/tools/tests/gen6/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 96   UIP: 98                         { align1 1Q };
-halt(8)         JIP: 2          UIP: 2                          { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 100 UIP: 102                        { align1 1H };
-halt(16)        JIP: 2          UIP: 2                          { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0      UIP: LABEL0              { align1 1Q };
+halt(8)         JIP: LABEL1            UIP: LABEL1              { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0     UIP: LABEL0              { align1 1H };
+halt(16)        JIP: LABEL0            UIP: LABEL0              { align1 1H };
+LABEL0:

diff --git a/src/intel/tools/tests/gen6/halt.expected b/src/intel/tools/tests/gen6/halt.expected
index b5b612af45d3abbd41d1206b43dad8eae7ec01ee..f76a4b179f744c0a9b7d62abfdeab7e040a31124 100644 (file)
--- a/src/intel/tools/tests/gen6/halt.expected
+++ b/src/intel/tools/tests/gen6/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 84 1c 00 20 00 00 8d 02 60 00 62 00
+2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
 2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
-2a 00 96 00 84 1c 00 20 00 00 8d 02 64 00 66 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
 2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen6/if.asm b/src/intel/tools/tests/gen6/if.asm
index 532dbda784e359bfa509b91aea7264aea0bdd29d..958a2d6eb205f6a854596defd6d1fec19df4222f 100644 (file)
--- a/src/intel/tools/tests/gen6/if.asm
+++ b/src/intel/tools/tests/gen6/if.asm
@@ -1,6 +1,8 @@
-(+f0.0) if(8)   JIP: 84                                         { align16 1Q };
-(+f0.0) if(8)   JIP: 32                                         { align1 1Q };
-(+f0.0) if(16)  JIP: 32                                         { align1 1H };
-(+f0.0.x) if(8) JIP: 18                                         { align16 1Q };
-(-f0.0) if(8)   JIP: 12                                         { align1 1Q };
-(-f0.0) if(16)  JIP: 12                                         { align1 1H };
+(+f0.0) if(8)   JIP: LABEL0                                     { align16 1Q };
+LABEL0:
+(+f0.0) if(8)   JIP: LABEL1                                     { align1 1Q };
+(+f0.0) if(16)  JIP: LABEL1                                     { align1 1H };
+(+f0.0.x) if(8) JIP: LABEL1                                     { align16 1Q };
+(-f0.0) if(8)   JIP: LABEL1                                     { align1 1Q };
+(-f0.0) if(16)  JIP: LABEL1                                     { align1 1H };
+LABEL1:

diff --git a/src/intel/tools/tests/gen6/if.expected b/src/intel/tools/tests/gen6/if.expected
index e5a2666c0d6709531a8fd06f38b9132400db2012..65c43f9787dbd56d830a03b480768bf7c218de96 100644 (file)
--- a/src/intel/tools/tests/gen6/if.expected
+++ b/src/intel/tools/tests/gen6/if.expected
@@ -1,6 +1,6 @@
-22 01 61 00 8f 10 54 00 04 00 0e 00 04 00 0e 00
-22 00 61 00 8f 10 20 00 00 00 00 00 00 00 00 00
-22 00 81 00 8f 10 20 00 00 00 00 00 00 00 00 00
-22 01 62 00 8f 10 12 00 04 00 0e 00 04 00 0e 00
-22 00 71 00 8f 10 0c 00 00 00 00 00 00 00 00 00
-22 00 91 00 8f 10 0c 00 00 00 00 00 00 00 00 00
+22 01 61 00 8f 10 02 00 04 00 0e 00 04 00 0e 00
+22 00 61 00 8f 10 0a 00 00 00 00 00 00 00 00 00
+22 00 81 00 8f 10 08 00 00 00 00 00 00 00 00 00
+22 01 62 00 8f 10 06 00 04 00 0e 00 04 00 0e 00
+22 00 71 00 8f 10 04 00 00 00 00 00 00 00 00 00
+22 00 91 00 8f 10 02 00 00 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen6/while.asm b/src/intel/tools/tests/gen6/while.asm
index 0df3ed79922e557b5c12e0ae3732e27cb2a69d45..df993482ba330c387049d4eab26d12d9bf2e5176 100644 (file)
--- a/src/intel/tools/tests/gen6/while.asm
+++ b/src/intel/tools/tests/gen6/while.asm
@@ -1,6 +1,7 @@
-while(8)        JIP: -76                                        { align16 1Q };
-while(8)        JIP: -108                                       { align1 1Q };
-while(16)       JIP: -108                                       { align1 1H };
-(-f0.0) while(8) JIP: -48                                       { align1 1Q };
-(-f0.0) while(16) JIP: -48                                      { align1 1H };
-(-f0.0.x) while(8) JIP: -48                                     { align16 1Q };
+LABEL0:
+while(8)        JIP: LABEL0                                     { align16 1Q };
+while(8)        JIP: LABEL0                                     { align1 1Q };
+while(16)       JIP: LABEL0                                     { align1 1H };
+(-f0.0) while(8) JIP: LABEL0                                    { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0                                   { align1 1H };
+(-f0.0.x) while(8) JIP: LABEL0                                  { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/while.expected b/src/intel/tools/tests/gen6/while.expected
index 4ea711e07b8d657b823d9941e18be7391a5e2979..35f4eb4dbf7171b525f4092942f45b1658487262 100644 (file)
--- a/src/intel/tools/tests/gen6/while.expected
+++ b/src/intel/tools/tests/gen6/while.expected
@@ -1,6 +1,6 @@
-27 01 60 00 8f 10 b4 ff 04 00 6e 00 04 00 6e 00
-27 00 60 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00
-27 00 80 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00
-27 00 71 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00
-27 00 91 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00
-27 01 72 00 8f 10 d0 ff 04 00 6e 00 04 00 6e 00
+27 01 60 00 8f 10 00 00 04 00 6e 00 04 00 6e 00
+27 00 60 00 8f 10 fe ff 00 00 8d 00 00 00 8d 00
+27 00 80 00 8f 10 fc ff 00 00 8d 00 00 00 8d 00
+27 00 71 00 8f 10 fa ff 00 00 8d 00 00 00 8d 00
+27 00 91 00 8f 10 f8 ff 00 00 8d 00 00 00 8d 00
+27 01 72 00 8f 10 f6 ff 04 00 6e 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen7.5/break.asm b/src/intel/tools/tests/gen7.5/break.asm
index fb3fb5c1ec2b0d5ce9b037cb579a8a4b9052b1e5..d4c7619de6c5394ae9d0dbdea8d9aade28e79e84 100644 (file)
--- a/src/intel/tools/tests/gen7.5/break.asm
+++ b/src/intel/tools/tests/gen7.5/break.asm
@@ -1,6 +1,8 @@
-break(8)        JIP: 2          UIP: 8                          { align1 1Q };
-break(16)       JIP: 2          UIP: 8                          { align1 1H };
-break(8)        JIP: 2          UIP: 10                         { align16 1Q };
-(+f0.0) break(8) JIP: 4         UIP: 10                         { align1 1Q };
-(+f0.0) break(16) JIP: 4        UIP: 10                         { align1 1H };
-(+f0.0.x) break(8) JIP: 110     UIP: 110                        { align16 1Q };
+break(8)        JIP: LABEL0          UIP: LABEL1                { align1 1Q };
+break(16)       JIP: LABEL0          UIP: LABEL1                { align1 1H };
+break(8)        JIP: LABEL0          UIP: LABEL1                { align16 1Q };
+LABEL0:
+(+f0.0) break(8) JIP: LABEL1         UIP: LABEL1                { align1 1Q };
+(+f0.0) break(16) JIP: LABEL1        UIP: LABEL1                { align1 1H };
+(+f0.0.x) break(8) JIP: LABEL1       UIP: LABEL1                { align16 1Q };
+LABEL1:

diff --git a/src/intel/tools/tests/gen7.5/break.expected b/src/intel/tools/tests/gen7.5/break.expected
index 8f8ccc8e73e386206a9703ecca5f1e12ae0a6c9d..309b5511939eaa7195c94beff7d5646c21ce473f 100644 (file)
--- a/src/intel/tools/tests/gen7.5/break.expected
+++ b/src/intel/tools/tests/gen7.5/break.expected
@@ -1,6 +1,6 @@
-28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 08 00
-28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 08 00
-28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0a 00
-28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
-28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
-28 01 62 00 84 1c 0f 20 04 00 6e 00 6e 00 6e 00
+28 00 60 00 84 1c 00 20 00 00 8d 00 06 00 0c 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 08 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7.5/cont.asm b/src/intel/tools/tests/gen7.5/cont.asm
index 7f7a9c4219699ad26667ae1ecc71775351975e5d..497a1155efc895f51540e75dbb0253e520c658aa 100644 (file)
--- a/src/intel/tools/tests/gen7.5/cont.asm
+++ b/src/intel/tools/tests/gen7.5/cont.asm
@@ -1,3 +1,6 @@
-cont(8)         JIP: 2          UIP: 8                          { align1 1Q };
-cont(16)        JIP: 2          UIP: 8                          { align1 1H };
-cont(8)         JIP: 2          UIP: 8                          { align16 1Q };
+cont(8)         JIP: LABEL0          UIP: LABEL2                { align1 1Q };
+LABEL0:
+cont(16)        JIP: LABEL1          UIP: LABEL2                { align1 1H };
+LABEL1:
+cont(8)         JIP: LABEL2          UIP: LABEL2                { align16 1Q };
+LABEL2:

diff --git a/src/intel/tools/tests/gen7.5/cont.expected b/src/intel/tools/tests/gen7.5/cont.expected
index a8376c2f2d577e0bf70e0d2ef050ab32adffded9..704ea3afd86be4ccb547346a1c64dd2347c8ed59 100644 (file)
--- a/src/intel/tools/tests/gen7.5/cont.expected
+++ b/src/intel/tools/tests/gen7.5/cont.expected
@@ -1,3 +1,3 @@
-29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00
-29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00
-29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00
+29 00 60 00 00 1c 00 34 00 14 60 00 02 00 06 00
+29 00 80 00 00 1c 00 34 00 14 60 00 02 00 04 00
+29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7.5/else.asm b/src/intel/tools/tests/gen7.5/else.asm
index 080628a3500328e4bc109228d00a102a3410a839..794e4afe178a9f298ed99d5a88b94d6fc05b268b 100644 (file)
--- a/src/intel/tools/tests/gen7.5/else.asm
+++ b/src/intel/tools/tests/gen7.5/else.asm
@@ -1,3 +1,4 @@
-else(8)         JIP: 4                                          { align16 1Q };
-else(8)         JIP: 72                                         { align1 1Q };
-else(16)        JIP: 72                                         { align1 1H };
+else(8)         JIP: LABEL0                                     { align16 1Q };
+else(8)         JIP: LABEL0                                     { align1 1Q };
+else(16)        JIP: LABEL0                                     { align1 1H };
+LABEL0:
\ No newline at end of file

diff --git a/src/intel/tools/tests/gen7.5/else.expected b/src/intel/tools/tests/gen7.5/else.expected
index f780798a61f16053873e296e37c2def709225b89..4e694cc8c1b78fa65dbef67abe005e6ab650603d 100644 (file)
--- a/src/intel/tools/tests/gen7.5/else.expected
+++ b/src/intel/tools/tests/gen7.5/else.expected
@@ -1,3 +1,3 @@
-24 01 60 00 84 3c 0f 20 04 00 6e 00 04 00 00 00
-24 00 60 00 84 3c 00 20 00 00 8d 00 48 00 00 00
-24 00 80 00 84 3c 00 20 00 00 8d 00 48 00 00 00
+24 01 60 00 84 3c 0f 20 04 00 6e 00 06 00 00 00
+24 00 60 00 84 3c 00 20 00 00 8d 00 04 00 00 00
+24 00 80 00 84 3c 00 20 00 00 8d 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/endif.asm b/src/intel/tools/tests/gen7.5/endif.asm
index 45955072e6a59d31d872f1fe1ab06c66b2af606e..e1dc0ebdbd818bacfff31325dd3447715391131a 100644 (file)
--- a/src/intel/tools/tests/gen7.5/endif.asm
+++ b/src/intel/tools/tests/gen7.5/endif.asm
@@ -1,3 +1,5 @@
-endif(8)        JIP: 6                                          { align1 1Q };
-endif(16)       JIP: 6                                          { align1 1H };
-endif(8)        JIP: 2                                          { align16 1Q };
+endif(8)        JIP: LABEL0                                          { align1 1Q };
+LABEL0:
+endif(16)       JIP: LABEL1                                          { align1 1H };
+endif(8)        JIP: LABEL1                                          { align16 1Q };
+LABEL1:
\ No newline at end of file

diff --git a/src/intel/tools/tests/gen7.5/endif.expected b/src/intel/tools/tests/gen7.5/endif.expected
index 73a60a31c4656b68bcc6c5967eafb2fd024f914c..5d3b34d2cdd631083e6f0edd2f04e39e36e0af2a 100644 (file)
--- a/src/intel/tools/tests/gen7.5/endif.expected
+++ b/src/intel/tools/tests/gen7.5/endif.expected
@@ -1,3 +1,3 @@
-25 00 60 00 84 3c 00 20 00 00 8d 00 06 00 00 00
-25 00 80 00 84 3c 00 20 00 00 8d 00 06 00 00 00
+25 00 60 00 84 3c 00 20 00 00 8d 00 02 00 00 00
+25 00 80 00 84 3c 00 20 00 00 8d 00 04 00 00 00
 25 01 60 00 84 3c 0f 20 04 00 6e 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/halt.asm b/src/intel/tools/tests/gen7.5/halt.asm
index 71ad27b5aa598bd51d48c2e719226fda428fe0fd..5f29e88c57cf7730dea705a7da83ea3ce8e7e344 100644 (file)
--- a/src/intel/tools/tests/gen7.5/halt.asm
+++ b/src/intel/tools/tests/gen7.5/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 72   UIP: 74                         { align1 1Q };
-halt(8)         JIP: 2          UIP: 2                          { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 72  UIP: 74                         { align1 1H };
-halt(16)        JIP: 2          UIP: 2                          { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0      UIP: LABEL0              { align1 1Q };
+halt(8)         JIP: LABEL1            UIP: LABEL1              { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0     UIP: LABEL0              { align1 1H };
+halt(16)        JIP: LABEL0            UIP: LABEL0              { align1 1H };
+LABEL0:

diff --git a/src/intel/tools/tests/gen7.5/halt.expected b/src/intel/tools/tests/gen7.5/halt.expected
index 84b32b1cd9ec443c001e56ba510cd8ee80241e8f..f76a4b179f744c0a9b7d62abfdeab7e040a31124 100644 (file)
--- a/src/intel/tools/tests/gen7.5/halt.expected
+++ b/src/intel/tools/tests/gen7.5/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
 2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
-2a 00 96 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
 2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7.5/if.asm b/src/intel/tools/tests/gen7.5/if.asm
index 0ebd44de6fdf8e31512a7e320fbaaf85e3fd7096..596e8edb6bc6472e897cf9b341f6e91d328867bd 100644 (file)
--- a/src/intel/tools/tests/gen7.5/if.asm
+++ b/src/intel/tools/tests/gen7.5/if.asm
@@ -1,6 +1,9 @@
-(-f0.0) if(8)   JIP: 8          UIP: 8                          { align1 1Q };
-(-f0.0) if(16)  JIP: 8          UIP: 8                          { align1 1H };
-(+f0.0.x) if(8) JIP: 18         UIP: 18                         { align16 1Q };
-(+f0.0) if(8)   JIP: 14         UIP: 14                         { align16 1Q };
-(+f0.0) if(8)   JIP: 12         UIP: 82                         { align1 1Q };
-(+f0.0) if(16)  JIP: 12         UIP: 82                         { align1 1H };
+(-f0.0) if(8)   JIP: LABEL0     UIP: LABEL2                     { align1 1Q };
+LABEL0:
+(-f0.0) if(16)  JIP: LABEL2     UIP: LABEL1                     { align1 1H };
+(+f0.0.x) if(8) JIP: LABEL2     UIP: LABEL1                     { align16 1Q };
+LABEL1:
+(+f0.0) if(8)   JIP: LABEL2     UIP: LABEL2                     { align16 1Q };
+(+f0.0) if(8)   JIP: LABEL2     UIP: LABEL2                     { align1 1Q };
+(+f0.0) if(16)  JIP: LABEL2     UIP: LABEL2                     { align1 1H };
+LABEL2:

diff --git a/src/intel/tools/tests/gen7.5/if.expected b/src/intel/tools/tests/gen7.5/if.expected
index d2bccde3c43a96c0a339f8c75334ede644cd00fb..2cb44c196a28c179cf586d109be1b3119631f953 100644 (file)
--- a/src/intel/tools/tests/gen7.5/if.expected
+++ b/src/intel/tools/tests/gen7.5/if.expected
@@ -1,6 +1,6 @@
-22 00 71 00 84 3c 00 20 00 00 00 00 08 00 08 00
-22 00 91 00 84 3c 00 20 00 00 00 00 08 00 08 00
-22 01 62 00 84 3c 0f 20 04 00 0e 00 12 00 12 00
-22 01 61 00 84 3c 0f 20 04 00 0e 00 0e 00 0e 00
-22 00 61 00 84 3c 00 20 00 00 00 00 0c 00 52 00
-22 00 81 00 84 3c 00 20 00 00 00 00 0c 00 52 00
+22 00 71 00 84 3c 00 20 00 00 00 00 02 00 0c 00
+22 00 91 00 84 3c 00 20 00 00 00 00 0a 00 04 00
+22 01 62 00 84 3c 0f 20 04 00 0e 00 08 00 02 00
+22 01 61 00 84 3c 0f 20 04 00 0e 00 06 00 06 00
+22 00 61 00 84 3c 00 20 00 00 00 00 04 00 04 00
+22 00 81 00 84 3c 00 20 00 00 00 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7.5/while.asm b/src/intel/tools/tests/gen7.5/while.asm
index a6d5abc72eb714b516fd77ea6f3367a3b9e65632..035f96500cd128a03ada4805efb1d62e6be7f613 100644 (file)
--- a/src/intel/tools/tests/gen7.5/while.asm
+++ b/src/intel/tools/tests/gen7.5/while.asm
@@ -1,6 +1,7 @@
-while(8)        JIP: -20                                        { align1 1Q };
-while(16)       JIP: -20                                        { align1 1H };
-while(8)        JIP: -30                                        { align16 1Q };
-(-f0.0) while(8) JIP: -48                                       { align1 1Q };
-(-f0.0) while(16) JIP: -48                                      { align1 1H };
-(-f0.0.x) while(8) JIP: -48                                     { align16 1Q };
+LABEL0:
+while(8)        JIP: LABEL0                                     { align1 1Q };
+while(16)       JIP: LABEL0                                     { align1 1H };
+while(8)        JIP: LABEL0                                     { align16 1Q };
+(-f0.0) while(8) JIP: LABEL0                                    { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0                                   { align1 1H };
+(-f0.0.x) while(8) JIP: LABEL0                                  { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/while.expected b/src/intel/tools/tests/gen7.5/while.expected
index 769cbaf573de9c9747147112b417fcc98b31b08b..2ea22612e15a43d2e651db93e9812637e63fdd5f 100644 (file)
--- a/src/intel/tools/tests/gen7.5/while.expected
+++ b/src/intel/tools/tests/gen7.5/while.expected
@@ -1,6 +1,6 @@
-27 00 60 00 84 3c 00 20 00 00 8d 00 ec ff 00 00
-27 00 80 00 84 3c 00 20 00 00 8d 00 ec ff 00 00
-27 01 60 00 84 3c 0f 20 04 00 6e 00 e2 ff 00 00
-27 00 71 00 84 3c 00 20 00 00 8d 00 d0 ff 00 00
-27 00 91 00 84 3c 00 20 00 00 8d 00 d0 ff 00 00
-27 01 72 00 84 3c 0f 20 04 00 6e 00 d0 ff 00 00
+27 00 60 00 84 3c 00 20 00 00 8d 00 00 00 00 00
+27 00 80 00 84 3c 00 20 00 00 8d 00 fe ff 00 00
+27 01 60 00 84 3c 0f 20 04 00 6e 00 fc ff 00 00
+27 00 71 00 84 3c 00 20 00 00 8d 00 fa ff 00 00
+27 00 91 00 84 3c 00 20 00 00 8d 00 f8 ff 00 00
+27 01 72 00 84 3c 0f 20 04 00 6e 00 f6 ff 00 00

diff --git a/src/intel/tools/tests/gen7/break.asm b/src/intel/tools/tests/gen7/break.asm
index 5a51f7a0a03457875f0e799404e87b4151cc45c9..ae39f9ad0a550d45d00bb996572493ed7ccc937d 100644 (file)
--- a/src/intel/tools/tests/gen7/break.asm
+++ b/src/intel/tools/tests/gen7/break.asm
@@ -1,6 +1,9 @@
-break(8)        JIP: 2          UIP: 40                         { align1 1Q };
-break(16)       JIP: 2          UIP: 48                         { align1 1H };
-(+f0.0.x) break(8) JIP: 110     UIP: 110                        { align16 1Q };
-(+f0.0) break(8) JIP: 2         UIP: 12                         { align1 1Q };
-(+f0.0) break(16) JIP: 2        UIP: 12                         { align1 1H };
-break(8)        JIP: 2          UIP: 38                         { align16 1Q };
+break(8)        JIP: LABEL0          UIP: LABEL0                { align1 1Q };
+LABEL0:
+break(16)       JIP: LABEL1          UIP: LABEL2                { align1 1H };
+(+f0.0.x) break(8) JIP: LABEL1       UIP: LABEL2                { align16 1Q };
+LABEL1:
+(+f0.0) break(8) JIP: LABEL2         UIP: LABEL2                { align1 1Q };
+(+f0.0) break(16) JIP: LABEL2        UIP: LABEL2                { align1 1H };
+break(8)        JIP: LABEL2          UIP: LABEL2                { align16 1Q };
+LABEL2:
\ No newline at end of file

diff --git a/src/intel/tools/tests/gen7/break.expected b/src/intel/tools/tests/gen7/break.expected
index 9cc7f8ae31f7bacbd028fc31cb0375b0a3cd07a3..7ded8f0068bcc33428a82ccd494117e25fc7575c 100644 (file)
--- a/src/intel/tools/tests/gen7/break.expected
+++ b/src/intel/tools/tests/gen7/break.expected
@@ -1,6 +1,6 @@
-28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 28 00
-28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 30 00
-28 01 62 00 84 1c 0f 20 04 00 6e 00 6e 00 6e 00
-28 00 61 00 84 1c 00 20 00 00 8d 00 02 00 0c 00
-28 00 81 00 84 1c 00 20 00 00 8d 00 02 00 0c 00
-28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 26 00
+28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 02 00 08 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 06 00 06 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 04 00
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7/else.asm b/src/intel/tools/tests/gen7/else.asm
index 71a09a3996d6819575a0ee2567464a921b3367c4..5450c0fd6cd69ebda47ee0b600c15719b633dea9 100644 (file)
--- a/src/intel/tools/tests/gen7/else.asm
+++ b/src/intel/tools/tests/gen7/else.asm
@@ -1,3 +1,4 @@
-else(8)         JIP: 12                                         { align1 1Q };
-else(16)        JIP: 12                                         { align1 1H };
-else(8)         JIP: 18                                         { align16 1Q };
+else(8)         JIP: LABEL0                                     { align1 1Q };
+else(16)        JIP: LABEL0                                     { align1 1H };
+else(8)         JIP: LABEL0                                     { align16 1Q };
+LABEL0:

diff --git a/src/intel/tools/tests/gen7/else.expected b/src/intel/tools/tests/gen7/else.expected
index 86cf63f42f2556a47dd3fbb19e243ecb32cf2634..1c4b3515961d19aebebc1e0b28d7c184c5564993 100644 (file)
--- a/src/intel/tools/tests/gen7/else.expected
+++ b/src/intel/tools/tests/gen7/else.expected
@@ -1,3 +1,3 @@
-24 00 60 00 84 3c 00 20 00 00 8d 00 0c 00 00 00
-24 00 80 00 84 3c 00 20 00 00 8d 00 0c 00 00 00
-24 01 60 00 84 3c 0f 20 04 00 6e 00 12 00 00 00
+24 00 60 00 84 3c 00 20 00 00 8d 00 06 00 00 00
+24 00 80 00 84 3c 00 20 00 00 8d 00 04 00 00 00
+24 01 60 00 84 3c 0f 20 04 00 6e 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen7/endif.asm b/src/intel/tools/tests/gen7/endif.asm
index b3a5066cb53d53f11bc591481becb89272d792e5..fc00e24535312b1b87ce459b282e4106d45f0808 100644 (file)
--- a/src/intel/tools/tests/gen7/endif.asm
+++ b/src/intel/tools/tests/gen7/endif.asm
@@ -1,3 +1,6 @@
-endif(8)        JIP: 2                                          { align16 1Q };
-endif(8)        JIP: 2                                          { align1 1Q };
-endif(16)       JIP: 2                                          { align1 1H };
+endif(8)        JIP: LABEL1                                     { align16 1Q };
+LABEL1:
+endif(8)        JIP: LABEL2                                     { align1 1Q };
+LABEL2:
+endif(16)       JIP: LABEL3                                     { align1 1H };
+LABEL3:

diff --git a/src/intel/tools/tests/gen7/halt.asm b/src/intel/tools/tests/gen7/halt.asm
index 0a06cc54da9a55d0d130eff84a67f7c20e1c54b5..5f29e88c57cf7730dea705a7da83ea3ce8e7e344 100644 (file)
--- a/src/intel/tools/tests/gen7/halt.asm
+++ b/src/intel/tools/tests/gen7/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 72   UIP: 74                         { align1 1Q };
-halt(8)         JIP: 2          UIP: 2                          { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 76  UIP: 78                         { align1 1H };
-halt(16)        JIP: 2          UIP: 2                          { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0      UIP: LABEL0              { align1 1Q };
+halt(8)         JIP: LABEL1            UIP: LABEL1              { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0     UIP: LABEL0              { align1 1H };
+halt(16)        JIP: LABEL0            UIP: LABEL0              { align1 1H };
+LABEL0:

diff --git a/src/intel/tools/tests/gen7/halt.expected b/src/intel/tools/tests/gen7/halt.expected
index edc7d9e179abb88a31f8171f4837beb3b4ddbe2d..f76a4b179f744c0a9b7d62abfdeab7e040a31124 100644 (file)
--- a/src/intel/tools/tests/gen7/halt.expected
+++ b/src/intel/tools/tests/gen7/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 76 00 84 1c 00 20 00 00 8d 02 08 00 08 00
 2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
-2a 00 96 00 84 1c 00 20 00 00 8d 02 4c 00 4e 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 04 00 04 00
 2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7/if.asm b/src/intel/tools/tests/gen7/if.asm
index e6d096d8f20e582db5ec17613030ae4f924c9b64..5e6bb07f3a6cba06a0f3824a0bc76e426c80845b 100644 (file)
--- a/src/intel/tools/tests/gen7/if.asm
+++ b/src/intel/tools/tests/gen7/if.asm
@@ -1,6 +1,9 @@
-(+f0.0.x) if(8) JIP: 18         UIP: 18                         { align16 1Q };
-(+f0.0) if(8)   JIP: 14         UIP: 14                         { align16 1Q };
-(+f0.0) if(8)   JIP: 32         UIP: 96                         { align1 1Q };
-(+f0.0) if(16)  JIP: 32         UIP: 96                         { align1 1H };
-(-f0.0) if(8)   JIP: 10         UIP: 10                         { align1 1Q };
-(-f0.0) if(16)  JIP: 10         UIP: 10                         { align1 1H };
+(+f0.0.x) if(8) JIP: LABEL0         UIP: LABEL2                 { align16 1Q };
+LABEL0:
+(+f0.0) if(8)   JIP: LABEL2         UIP: LABEL1                 { align16 1Q };
+(+f0.0) if(8)   JIP: LABEL2         UIP: LABEL1                 { align1 1Q };
+LABEL1:
+(+f0.0) if(16)  JIP: LABEL2         UIP: LABEL2                 { align1 1H };
+(-f0.0) if(8)   JIP: LABEL2         UIP: LABEL2                 { align1 1Q };
+(-f0.0) if(16)  JIP: LABEL2         UIP: LABEL2                 { align1 1H };
+LABEL2:

diff --git a/src/intel/tools/tests/gen7/if.expected b/src/intel/tools/tests/gen7/if.expected
index c08f2ff2568f85a110cf439feb5d5adb1d32adfc..e5e6c19c2b702100b4f14cf6fa1c61072ca8bb9a 100644 (file)
--- a/src/intel/tools/tests/gen7/if.expected
+++ b/src/intel/tools/tests/gen7/if.expected
@@ -1,6 +1,6 @@
-22 01 62 00 84 3c 0f 20 04 00 0e 00 12 00 12 00
-22 01 61 00 84 3c 0f 20 04 00 0e 00 0e 00 0e 00
-22 00 61 00 84 3c 00 20 00 00 00 00 20 00 60 00
-22 00 81 00 84 3c 00 20 00 00 00 00 20 00 60 00
-22 00 71 00 84 3c 00 20 00 00 00 00 0a 00 0a 00
-22 00 91 00 84 3c 00 20 00 00 00 00 0a 00 0a 00
+22 01 62 00 84 3c 0f 20 04 00 0e 00 02 00 0c 00
+22 01 61 00 84 3c 0f 20 04 00 0e 00 0a 00 04 00
+22 00 61 00 84 3c 00 20 00 00 00 00 08 00 02 00
+22 00 81 00 84 3c 00 20 00 00 00 00 06 00 06 00
+22 00 71 00 84 3c 00 20 00 00 00 00 04 00 04 00
+22 00 91 00 84 3c 00 20 00 00 00 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7/while.asm b/src/intel/tools/tests/gen7/while.asm
index be4e182a6335df2ace31f5ae45453343333bb833..8465a910663466d64ee4a6473a18e5212829b709 100644 (file)
--- a/src/intel/tools/tests/gen7/while.asm
+++ b/src/intel/tools/tests/gen7/while.asm
@@ -1,5 +1,6 @@
-while(8)        JIP: -50                                        { align1 1Q };
-while(16)       JIP: -58                                        { align1 1H };
-while(8)        JIP: -8                                         { align16 1Q };
-(-f0.0) while(8) JIP: -10                                       { align1 1Q };
-(-f0.0) while(16) JIP: -10                                      { align1 1H };
+LABEL0:
+while(8)        JIP: LABEL0                                     { align1 1Q };
+while(16)       JIP: LABEL0                                     { align1 1H };
+while(8)        JIP: LABEL0                                     { align16 1Q };
+(-f0.0) while(8) JIP: LABEL0                                    { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0                                   { align1 1H };

diff --git a/src/intel/tools/tests/gen7/while.expected b/src/intel/tools/tests/gen7/while.expected
index 70dd598c4be731c90335f07a95c6379f4c08a3db..379819a609bdc9fa481102463c0dc27d572d1f61 100644 (file)
--- a/src/intel/tools/tests/gen7/while.expected
+++ b/src/intel/tools/tests/gen7/while.expected
@@ -1,5 +1,5 @@
-27 00 60 00 84 3c 00 20 00 00 8d 00 ce ff 00 00
-27 00 80 00 84 3c 00 20 00 00 8d 00 c6 ff 00 00
-27 01 60 00 84 3c 0f 20 04 00 6e 00 f8 ff 00 00
-27 00 71 00 84 3c 00 20 00 00 8d 00 f6 ff 00 00
-27 00 91 00 84 3c 00 20 00 00 8d 00 f6 ff 00 00
+27 00 60 00 84 3c 00 20 00 00 8d 00 00 00 00 00
+27 00 80 00 84 3c 00 20 00 00 8d 00 fe ff 00 00
+27 01 60 00 84 3c 0f 20 04 00 6e 00 fc ff 00 00
+27 00 71 00 84 3c 00 20 00 00 8d 00 fa ff 00 00
+27 00 91 00 84 3c 00 20 00 00 8d 00 f8 ff 00 00

diff --git a/src/intel/tools/tests/gen8/break.asm b/src/intel/tools/tests/gen8/break.asm
index 093ae61d5138326a4d24109002c6198ff767ba98..681b3d2c8a16c9cb421765961c1c606e1676fe00 100644 (file)
--- a/src/intel/tools/tests/gen8/break.asm
+++ b/src/intel/tools/tests/gen8/break.asm
@@ -1,4 +1,6 @@
-break(8)        JIP: 16         UIP: 64                         { align1 1Q };
-break(16)       JIP: 16         UIP: 64                         { align1 1H };
-(+f0.0) break(8) JIP: 32        UIP: 80                         { align1 1Q };
-(+f0.0) break(16) JIP: 32       UIP: 80                         { align1 1H };
+break(8)        JIP: LABEL0         UIP: LABEL1                 { align1 1Q };
+break(16)       JIP: LABEL0         UIP: LABEL1                 { align1 1H };
+LABEL0:
+(+f0.0) break(8) JIP: LABEL1        UIP: LABEL1                 { align1 1Q };
+(+f0.0) break(16) JIP: LABEL1       UIP: LABEL1                 { align1 1H };
+LABEL1:

diff --git a/src/intel/tools/tests/gen8/break.expected b/src/intel/tools/tests/gen8/break.expected
index 305af58e2ced6819169e4812113820e2babc4572..f5448cdbdf3aff3fa25838bfe0d1e133cd3eaa3c 100644 (file)
--- a/src/intel/tools/tests/gen8/break.expected
+++ b/src/intel/tools/tests/gen8/break.expected
@@ -1,4 +1,4 @@
-28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00
-28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00
-28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
-28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00
+28 00 60 00 20 0e 00 20 40 00 00 00 20 00 00 00
+28 00 80 00 20 0e 00 20 30 00 00 00 10 00 00 00
+28 00 61 00 20 0e 00 20 20 00 00 00 20 00 00 00
+28 00 81 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/cont.asm b/src/intel/tools/tests/gen8/cont.asm
index c5a194bace38b4e318b09b90867efc16300d8636..ca97a556e9c372002ff4094ed502b518e0bb328d 100644 (file)
--- a/src/intel/tools/tests/gen8/cont.asm
+++ b/src/intel/tools/tests/gen8/cont.asm
@@ -1,2 +1,4 @@
-cont(8)         JIP: 16         UIP: 64                         { align1 1Q };
-cont(16)        JIP: 16         UIP: 64                         { align1 1H };
+cont(8)         JIP: LABEL0         UIP: LABEL1                 { align1 1Q };
+LABEL0:
+cont(16)        JIP: LABEL1         UIP: LABEL1                 { align1 1H };
+LABEL1:

diff --git a/src/intel/tools/tests/gen8/cont.expected b/src/intel/tools/tests/gen8/cont.expected
index 83aa4f5e5e583f158034f27b30587f55d89ce6c6..d8036df8e1c85c8ea886a50aa334949fbda9223e 100644 (file)
--- a/src/intel/tools/tests/gen8/cont.expected
+++ b/src/intel/tools/tests/gen8/cont.expected
@@ -1,2 +1,2 @@
-29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00
-29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00
+29 00 60 00 00 0e 00 34 20 00 00 00 10 00 00 00
+29 00 80 00 00 0e 00 34 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/else.asm b/src/intel/tools/tests/gen8/else.asm
index 837df09e26e1126b92e6164d061dd62b0b7fb842..ce868a280cddad81ef467bee27a1c4ac3fd6e82b 100644 (file)
--- a/src/intel/tools/tests/gen8/else.asm
+++ b/src/intel/tools/tests/gen8/else.asm
@@ -1,3 +1,4 @@
-else(8)         JIP: 288        UIP: 288                        { align1 1Q };
-else(16)        JIP: 240        UIP: 240                        { align1 1H };
-else(32)        JIP: 144        UIP: 144                        { align1 };
+else(8)         JIP: LABEL0        UIP: LABEL0                  { align1 1Q };
+else(16)        JIP: LABEL0        UIP: LABEL0                  { align1 1H };
+else(32)        JIP: LABEL0        UIP: LABEL0                  { align1 };
+LABEL0:
\ No newline at end of file

diff --git a/src/intel/tools/tests/gen8/else.expected b/src/intel/tools/tests/gen8/else.expected
index 1394b4672b07a71bd0efb885cd3490cb7e26d1b2..c7834d75bcd673501c2ea86a8de569132cf282dc 100644 (file)
--- a/src/intel/tools/tests/gen8/else.expected
+++ b/src/intel/tools/tests/gen8/else.expected
@@ -1,3 +1,3 @@
-24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00
-24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00
-24 00 a0 00 20 0e 00 20 90 00 00 00 90 00 00 00
+24 00 60 00 20 0e 00 20 30 00 00 00 30 00 00 00
+24 00 80 00 20 0e 00 20 20 00 00 00 20 00 00 00
+24 00 a0 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/endif.asm b/src/intel/tools/tests/gen8/endif.asm
index bfd04eab63f9ff6a3fa815f797d67f0235713c05..206798e2de63b62cde72f643667eb0e463a1e3ef 100644 (file)
--- a/src/intel/tools/tests/gen8/endif.asm
+++ b/src/intel/tools/tests/gen8/endif.asm
@@ -1,3 +1,4 @@
-endif(8)        JIP: 80                                         { align1 1Q };
-endif(16)       JIP: 48                                         { align1 1H };
-endif(32)       JIP: 16                                         { align1 };
+endif(8)        JIP: LABEL0                                     { align1 1Q };
+endif(16)       JIP: LABEL0                                     { align1 1H };
+endif(32)       JIP: LABEL0                                     { align1 };
+LABEL0:

diff --git a/src/intel/tools/tests/gen8/endif.expected b/src/intel/tools/tests/gen8/endif.expected
index 898a1486c2dfd66ef3c65bf693c13c747640f470..5f6a9feba4033debe9394a3d0aeffddb15f68a86 100644 (file)
--- a/src/intel/tools/tests/gen8/endif.expected
+++ b/src/intel/tools/tests/gen8/endif.expected
@@ -1,3 +1,3 @@
-25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00
-25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 60 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 80 00 00 0e 00 00 00 00 00 08 20 00 00 00
 25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/halt.asm b/src/intel/tools/tests/gen8/halt.asm
index d84432603ea642319c87d3158c23e375bfa6a096..726d1917f8863b1a118eb16aee432cd58e436836 100644 (file)
--- a/src/intel/tools/tests/gen8/halt.asm
+++ b/src/intel/tools/tests/gen8/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 176  UIP: 192                        { align1 1Q };
-halt(8)         JIP: 16         UIP: 16                         { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 176 UIP: 192                        { align1 1H };
-halt(16)        JIP: 16         UIP: 16                         { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0      UIP: LABEL0              { align1 1Q };
+halt(8)         JIP: LABEL1            UIP: LABEL1              { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0     UIP: LABEL0              { align1 1H };
+halt(16)        JIP: LABEL0            UIP: LABEL0              { align1 1H };
+LABEL0:
\ No newline at end of file

diff --git a/src/intel/tools/tests/gen8/halt.expected b/src/intel/tools/tests/gen8/halt.expected
index 4e4573db43de7e9389b8dcea29c86bc89c1ecb1d..b0867fe7f818bb9464e669b8b024f76d441a2c1a 100644 (file)
--- a/src/intel/tools/tests/gen8/halt.expected
+++ b/src/intel/tools/tests/gen8/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 76 00 21 0e 00 20 40 00 00 00 40 00 00 00
 2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00
-2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 96 00 21 0e 00 20 20 00 00 00 20 00 00 00
 2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/if.asm b/src/intel/tools/tests/gen8/if.asm
index 5eb7b53fc64af5b73923c234f7ad2d1f5c1b381f..d6f8b84d75897d53a1f3620da37832879503d758 100644 (file)
--- a/src/intel/tools/tests/gen8/if.asm
+++ b/src/intel/tools/tests/gen8/if.asm
@@ -1,5 +1,7 @@
-(+f0.0) if(8)   JIP: 1376       UIP: 1392                       { align1 1Q };
-(-f0.0) if(8)   JIP: 4704       UIP: 4704                       { align1 1Q };
-(-f0.0) if(16)  JIP: 64         UIP: 64                         { align1 1H };
-(+f0.0) if(16)  JIP: 96         UIP: 320                        { align1 1H };
-(+f0.0) if(32)  JIP: 80         UIP: 80                         { align1 };
+(+f0.0) if(8)   JIP: LABEL0       UIP: LABEL1                   { align1 1Q };
+(-f0.0) if(8)   JIP: LABEL0       UIP: LABEL1                   { align1 1Q };
+LABEL0:
+(-f0.0) if(16)  JIP: LABEL1       UIP: LABEL1                 { align1 1H };
+(+f0.0) if(16)  JIP: LABEL1       UIP: LABEL1                 { align1 1H };
+(+f0.0) if(32)  JIP: LABEL1       UIP: LABEL1                 { align1 };
+LABEL1:

diff --git a/src/intel/tools/tests/gen8/if.expected b/src/intel/tools/tests/gen8/if.expected
index b2fc2852e600acbbb6252684f792e48774272b08..d11bebc1730e79f8abd50438d6d7b12dc87ac248 100644 (file)
--- a/src/intel/tools/tests/gen8/if.expected
+++ b/src/intel/tools/tests/gen8/if.expected
@@ -1,5 +1,5 @@
-22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00
-22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00
-22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00
-22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00
-22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00
+22 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
+22 00 71 00 20 0e 00 20 40 00 00 00 10 00 00 00
+22 00 91 00 20 0e 00 20 30 00 00 00 30 00 00 00
+22 00 81 00 20 0e 00 20 20 00 00 00 20 00 00 00
+22 00 a1 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/while.asm b/src/intel/tools/tests/gen8/while.asm
index 00bd8e1bff6c0591e8a8bda1b2a71b1e2334a180..7aaae755391171cf07691dd3d68736f6cd475625 100644 (file)
--- a/src/intel/tools/tests/gen8/while.asm
+++ b/src/intel/tools/tests/gen8/while.asm
@@ -1,4 +1,5 @@
-while(8)        JIP: -160                                       { align1 1Q };
-while(16)       JIP: -160                                       { align1 1H };
-(-f0.0) while(8) JIP: -384                                      { align1 1Q };
-(-f0.0) while(16) JIP: -384                                     { align1 1H };
+LABEL0:
+while(8)        JIP: LABEL0                                     { align1 1Q };
+while(16)       JIP: LABEL0                                     { align1 1H };
+(-f0.0) while(8) JIP: LABEL0                                    { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0                                   { align1 1H };

diff --git a/src/intel/tools/tests/gen8/while.expected b/src/intel/tools/tests/gen8/while.expected
index 5b0fd8538ab81299fc2f8e951f40140c25f14b1b..8b6c4da652f18beecfee93268a07b9fb8a7f9086 100644 (file)
--- a/src/intel/tools/tests/gen8/while.expected
+++ b/src/intel/tools/tests/gen8/while.expected
@@ -1,4 +1,4 @@
-27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff
-27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff
-27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff
-27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff
+27 00 60 00 20 0e 00 20 00 00 00 08 00 00 00 00
+27 00 80 00 20 0e 00 20 00 00 00 08 f0 ff ff ff
+27 00 71 00 20 0e 00 20 00 00 00 08 e0 ff ff ff
+27 00 91 00 20 0e 00 20 00 00 00 08 d0 ff ff ff

diff --git a/src/intel/tools/tests/gen9/break.asm b/src/intel/tools/tests/gen9/break.asm
index 093ae61d5138326a4d24109002c6198ff767ba98..681b3d2c8a16c9cb421765961c1c606e1676fe00 100644 (file)
--- a/src/intel/tools/tests/gen9/break.asm
+++ b/src/intel/tools/tests/gen9/break.asm
@@ -1,4 +1,6 @@
-break(8)        JIP: 16         UIP: 64                         { align1 1Q };
-break(16)       JIP: 16         UIP: 64                         { align1 1H };
-(+f0.0) break(8) JIP: 32        UIP: 80                         { align1 1Q };
-(+f0.0) break(16) JIP: 32       UIP: 80                         { align1 1H };
+break(8)        JIP: LABEL0         UIP: LABEL1                 { align1 1Q };
+break(16)       JIP: LABEL0         UIP: LABEL1                 { align1 1H };
+LABEL0:
+(+f0.0) break(8) JIP: LABEL1        UIP: LABEL1                 { align1 1Q };
+(+f0.0) break(16) JIP: LABEL1       UIP: LABEL1                 { align1 1H };
+LABEL1:

diff --git a/src/intel/tools/tests/gen9/break.expected b/src/intel/tools/tests/gen9/break.expected
index 305af58e2ced6819169e4812113820e2babc4572..f5448cdbdf3aff3fa25838bfe0d1e133cd3eaa3c 100644 (file)
--- a/src/intel/tools/tests/gen9/break.expected
+++ b/src/intel/tools/tests/gen9/break.expected
@@ -1,4 +1,4 @@
-28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00
-28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00
-28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
-28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00
+28 00 60 00 20 0e 00 20 40 00 00 00 20 00 00 00
+28 00 80 00 20 0e 00 20 30 00 00 00 10 00 00 00
+28 00 61 00 20 0e 00 20 20 00 00 00 20 00 00 00
+28 00 81 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/cont.asm b/src/intel/tools/tests/gen9/cont.asm
index c5a194bace38b4e318b09b90867efc16300d8636..ca97a556e9c372002ff4094ed502b518e0bb328d 100644 (file)
--- a/src/intel/tools/tests/gen9/cont.asm
+++ b/src/intel/tools/tests/gen9/cont.asm
@@ -1,2 +1,4 @@
-cont(8)         JIP: 16         UIP: 64                         { align1 1Q };
-cont(16)        JIP: 16         UIP: 64                         { align1 1H };
+cont(8)         JIP: LABEL0         UIP: LABEL1                 { align1 1Q };
+LABEL0:
+cont(16)        JIP: LABEL1         UIP: LABEL1                 { align1 1H };
+LABEL1:

diff --git a/src/intel/tools/tests/gen9/cont.expected b/src/intel/tools/tests/gen9/cont.expected
index 83aa4f5e5e583f158034f27b30587f55d89ce6c6..d8036df8e1c85c8ea886a50aa334949fbda9223e 100644 (file)
--- a/src/intel/tools/tests/gen9/cont.expected
+++ b/src/intel/tools/tests/gen9/cont.expected
@@ -1,2 +1,2 @@
-29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00
-29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00
+29 00 60 00 00 0e 00 34 20 00 00 00 10 00 00 00
+29 00 80 00 00 0e 00 34 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/else.asm b/src/intel/tools/tests/gen9/else.asm
index 83246247c552ac624ede8f59111af60485fa0ad1..ce868a280cddad81ef467bee27a1c4ac3fd6e82b 100644 (file)
--- a/src/intel/tools/tests/gen9/else.asm
+++ b/src/intel/tools/tests/gen9/else.asm
@@ -1,3 +1,4 @@
-else(8)         JIP: 288        UIP: 288                        { align1 1Q };
-else(16)        JIP: 240        UIP: 240                        { align1 1H };
-else(32)        JIP: 272        UIP: 272                        { align1 };
+else(8)         JIP: LABEL0        UIP: LABEL0                  { align1 1Q };
+else(16)        JIP: LABEL0        UIP: LABEL0                  { align1 1H };
+else(32)        JIP: LABEL0        UIP: LABEL0                  { align1 };
+LABEL0:
\ No newline at end of file

diff --git a/src/intel/tools/tests/gen9/else.expected b/src/intel/tools/tests/gen9/else.expected
index 44503c7f4275020efb9660986b78ae2cbd746318..c7834d75bcd673501c2ea86a8de569132cf282dc 100644 (file)
--- a/src/intel/tools/tests/gen9/else.expected
+++ b/src/intel/tools/tests/gen9/else.expected
@@ -1,3 +1,3 @@
-24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00
-24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00
-24 00 a0 00 20 0e 00 20 10 01 00 00 10 01 00 00
+24 00 60 00 20 0e 00 20 30 00 00 00 30 00 00 00
+24 00 80 00 20 0e 00 20 20 00 00 00 20 00 00 00
+24 00 a0 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/endif.asm b/src/intel/tools/tests/gen9/endif.asm
index bfd04eab63f9ff6a3fa815f797d67f0235713c05..206798e2de63b62cde72f643667eb0e463a1e3ef 100644 (file)
--- a/src/intel/tools/tests/gen9/endif.asm
+++ b/src/intel/tools/tests/gen9/endif.asm
@@ -1,3 +1,4 @@
-endif(8)        JIP: 80                                         { align1 1Q };
-endif(16)       JIP: 48                                         { align1 1H };
-endif(32)       JIP: 16                                         { align1 };
+endif(8)        JIP: LABEL0                                     { align1 1Q };
+endif(16)       JIP: LABEL0                                     { align1 1H };
+endif(32)       JIP: LABEL0                                     { align1 };
+LABEL0:

diff --git a/src/intel/tools/tests/gen9/endif.expected b/src/intel/tools/tests/gen9/endif.expected
index 898a1486c2dfd66ef3c65bf693c13c747640f470..5f6a9feba4033debe9394a3d0aeffddb15f68a86 100644 (file)
--- a/src/intel/tools/tests/gen9/endif.expected
+++ b/src/intel/tools/tests/gen9/endif.expected
@@ -1,3 +1,3 @@
-25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00
-25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 60 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 80 00 00 0e 00 00 00 00 00 08 20 00 00 00
 25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/halt.asm b/src/intel/tools/tests/gen9/halt.asm
index d84432603ea642319c87d3158c23e375bfa6a096..726d1917f8863b1a118eb16aee432cd58e436836 100644 (file)
--- a/src/intel/tools/tests/gen9/halt.asm
+++ b/src/intel/tools/tests/gen9/halt.asm
@@ -1,4 +1,6 @@
-(-f0.1.any4h) halt(8) JIP: 176  UIP: 192                        { align1 1Q };
-halt(8)         JIP: 16         UIP: 16                         { align1 1Q };
-(-f0.1.any4h) halt(16) JIP: 176 UIP: 192                        { align1 1H };
-halt(16)        JIP: 16         UIP: 16                         { align1 1H };
+(-f0.1.any4h) halt(8) JIP: LABEL0      UIP: LABEL0              { align1 1Q };
+halt(8)         JIP: LABEL1            UIP: LABEL1              { align1 1Q };
+LABEL1:
+(-f0.1.any4h) halt(16) JIP: LABEL0     UIP: LABEL0              { align1 1H };
+halt(16)        JIP: LABEL0            UIP: LABEL0              { align1 1H };
+LABEL0:
\ No newline at end of file

diff --git a/src/intel/tools/tests/gen9/halt.expected b/src/intel/tools/tests/gen9/halt.expected
index 4e4573db43de7e9389b8dcea29c86bc89c1ecb1d..b0867fe7f818bb9464e669b8b024f76d441a2c1a 100644 (file)
--- a/src/intel/tools/tests/gen9/halt.expected
+++ b/src/intel/tools/tests/gen9/halt.expected
@@ -1,4 +1,4 @@
-2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 76 00 21 0e 00 20 40 00 00 00 40 00 00 00
 2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00
-2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 96 00 21 0e 00 20 20 00 00 00 20 00 00 00
 2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/if.asm b/src/intel/tools/tests/gen9/if.asm
index 5eb7b53fc64af5b73923c234f7ad2d1f5c1b381f..e5192c41248c3d9829d85b9a061f609b9266e2fa 100644 (file)
--- a/src/intel/tools/tests/gen9/if.asm
+++ b/src/intel/tools/tests/gen9/if.asm
@@ -1,5 +1,7 @@
-(+f0.0) if(8)   JIP: 1376       UIP: 1392                       { align1 1Q };
-(-f0.0) if(8)   JIP: 4704       UIP: 4704                       { align1 1Q };
-(-f0.0) if(16)  JIP: 64         UIP: 64                         { align1 1H };
-(+f0.0) if(16)  JIP: 96         UIP: 320                        { align1 1H };
-(+f0.0) if(32)  JIP: 80         UIP: 80                         { align1 };
+(+f0.0) if(8)   JIP: LABEL0       UIP: LABEL1                   { align1 1Q };
+(-f0.0) if(8)   JIP: LABEL0       UIP: LABEL1                   { align1 1Q };
+LABEL0:
+(-f0.0) if(16)  JIP: LABEL1       UIP: LABEL1                   { align1 1H };
+(+f0.0) if(16)  JIP: LABEL1       UIP: LABEL1                   { align1 1H };
+(+f0.0) if(32)  JIP: LABEL1       UIP: LABEL1                   { align1 };
+LABEL1:

diff --git a/src/intel/tools/tests/gen9/if.expected b/src/intel/tools/tests/gen9/if.expected
index b2fc2852e600acbbb6252684f792e48774272b08..d11bebc1730e79f8abd50438d6d7b12dc87ac248 100644 (file)
--- a/src/intel/tools/tests/gen9/if.expected
+++ b/src/intel/tools/tests/gen9/if.expected
@@ -1,5 +1,5 @@
-22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00
-22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00
-22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00
-22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00
-22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00
+22 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
+22 00 71 00 20 0e 00 20 40 00 00 00 10 00 00 00
+22 00 91 00 20 0e 00 20 30 00 00 00 30 00 00 00
+22 00 81 00 20 0e 00 20 20 00 00 00 20 00 00 00
+22 00 a1 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/while.asm b/src/intel/tools/tests/gen9/while.asm
index 00bd8e1bff6c0591e8a8bda1b2a71b1e2334a180..7aaae755391171cf07691dd3d68736f6cd475625 100644 (file)
--- a/src/intel/tools/tests/gen9/while.asm
+++ b/src/intel/tools/tests/gen9/while.asm
@@ -1,4 +1,5 @@
-while(8)        JIP: -160                                       { align1 1Q };
-while(16)       JIP: -160                                       { align1 1H };
-(-f0.0) while(8) JIP: -384                                      { align1 1Q };
-(-f0.0) while(16) JIP: -384                                     { align1 1H };
+LABEL0:
+while(8)        JIP: LABEL0                                     { align1 1Q };
+while(16)       JIP: LABEL0                                     { align1 1H };
+(-f0.0) while(8) JIP: LABEL0                                    { align1 1Q };
+(-f0.0) while(16) JIP: LABEL0                                   { align1 1H };

diff --git a/src/intel/tools/tests/gen9/while.expected b/src/intel/tools/tests/gen9/while.expected
index 5b0fd8538ab81299fc2f8e951f40140c25f14b1b..8b6c4da652f18beecfee93268a07b9fb8a7f9086 100644 (file)
--- a/src/intel/tools/tests/gen9/while.expected
+++ b/src/intel/tools/tests/gen9/while.expected
@@ -1,4 +1,4 @@
-27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff
-27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff
-27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff
-27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff
+27 00 60 00 20 0e 00 20 00 00 00 08 00 00 00 00
+27 00 80 00 20 0e 00 20 00 00 00 08 f0 ff ff ff
+27 00 71 00 20 0e 00 20 00 00 00 08 e0 ff ff ff
+27 00 91 00 20 0e 00 20 00 00 00 08 d0 ff ff ff