test_countzero.py: rename output files

diff --git a/src/soc/fu/logical/test/test_countzero.py b/src/soc/fu/logical/test/test_countzero.py
index 3a78fd8f339d3a3cdf8a0d529c20c4b9bc222b54..62376ae67c06cdfba0bddcdf77ba0d301c8dc634 100644 (file)
--- a/src/soc/fu/logical/test/test_countzero.py
+++ b/src/soc/fu/logical/test/test_countzero.py
@@ -87,7 +87,7 @@ class ZeroCounterTestCase(FHDLTestCase):
         sim.add_process(process)  # or sim.add_sync_process(process), see below
 
         # run test and write vcd
-        fn = "genullnau"
+        fn = "countzero"
         with sim.write_vcd(fn+".vcd", fn+".gtkw", traces=dut.ports()):
             sim.run()