argh, found the blackbox problem: yosys is "doing the right thing" and

identifying spblock as a cell (there are 4 used, therefore it gets identified
as a cell).
also because the blackbox is empty, yosys is optimising it out.
therefore, solution: put something (q = d) into the blackbox, and make
4 each with different names.
yes, it is awful, but it works

diff --git a/experiments9/Makefile b/experiments9/Makefile
index 9bf47a844e7ed6dd33a4c6d1e6bafca191d1b79b..c236f5b62389b2ed9e1421fb872179b02b73adf0 100755 (executable)
--- a/experiments9/Makefile
+++ b/experiments9/Makefile
@@ -3,7 +3,11 @@
        PHYSICAL_SYNTHESIS = Coriolis
                DESIGN_KIT = cmos45
             YOSYS_FLATTEN = No
-         YOSYS_BLACKBOXES = pll spblock512w64b8w
+         YOSYS_BLACKBOXES = pll \
+                           spblock512w64b8w_0 \
+                           spblock512w64b8w_1 \
+                           spblock512w64b8w_2 \
+                           spblock512w64b8w_3
 #            YOSYS_SET_TOP = Yes
                     CHIP  = chip
                     CORE  = ls180

diff --git a/experiments9/build_full_4ksram.sh b/experiments9/build_full_4ksram.sh
index 98443099ca5a631a810efe5d634fff7664668688..ef2257d26d77c2f1106bd52befafe25d22de06aa 100755 (executable)
--- a/experiments9/build_full_4ksram.sh
+++ b/experiments9/build_full_4ksram.sh
@@ -24,7 +24,7 @@ rm *.vst *.ap
 cp non_generated/full_core_4_4ksram_ls180.v ls180.v
 cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v
 cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v
-cp non_generated/spblock*.v* .
+cp non_generated/spblock*.v .
 cp non_generated/pll.v .
 touch mem.init
 touch mem_1.init

diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
index 0715492fb506f0a233e2727a240347f512f510ca..0d5f7fe682135553edec69e586059d03e563de4e 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v
+++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
@@ -193401,7 +193401,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac
   assign \$1  = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb;
   always @(posedge clk)
     sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
-  spblock_512w64b8w \U$$0  (
+  spblock512w64b8w_0 spblock512w64b8w_0 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193545,7 +193545,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac
   assign \$1  = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb;
   always @(posedge clk)
     sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
-  spblock_512w64b8w \U$$0  (
+   spblock512w64b8w_1 spblock512w64b8w_1 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193689,7 +193689,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac
   assign \$1  = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb;
   always @(posedge clk)
     sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
-  spblock_512w64b8w \U$$0  (
+   spblock512w64b8w_2 spblock512w64b8w_2 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193833,7 +193833,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac
   assign \$1  = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb;
   always @(posedge clk)
     sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
-  spblock_512w64b8w \U$$0  (
+   spblock512w64b8w_3 spblock512w64b8w_3 (
     .a(a),
     .clk(clk),
     .d(d),

diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.v b/experiments9/non_generated/full_core_4_4ksram_ls180.v
index 2eef8b90efc2721347812b1c741379f497294031..c57eb511fc1d3e2f0ecb32aa1e466947b7bd3047 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_ls180.v
+++ b/experiments9/non_generated/full_core_4_4ksram_ls180.v
@@ -1,3 +1,6 @@
 `include "litex_ls180.v"
-`include "spblock512w64b8w.v"
 `include "libresoc.v"
+//`include "spblock512w64b8w_0.v"
+//`include "spblock512w64b8w_1.v"
+//`include "spblock512w64b8w_2.v"
+//`include "spblock512w64b8w_3.v"

diff --git a/experiments9/non_generated/spblock512w64b8w.v b/experiments9/non_generated/spblock512w64b8w.v
index a1111274a15de89a1d8f3d83c27f285f55ee62ca..3920d52f84a460c06d513518ce700b832c40142c 100644 (file)
--- a/experiments9/non_generated/spblock512w64b8w.v
+++ b/experiments9/non_generated/spblock512w64b8w.v
@@ -1,9 +1,9 @@
-(* blackbox = 1 *)
 module spblock512w64b8w(a, d, q, we, clk);
        input [8:0] a;
        input [63:0] d;
        output [63:0] q;
        input [7:0] we;
        input clk;
+assign q = d;
 endmodule // SPBlock_512W64B8W
 

diff --git a/experiments9/non_generated/spblock512w64b8w_0.v b/experiments9/non_generated/spblock512w64b8w_0.v
new file mode 100644 (file)
index 0000000..24e72a4
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w_0.v
@@ -0,0 +1,11 @@
+(* \nmigen.hierarchy  = "test_issuer.ti.sram4k_0.spblock512w64b8w_0" *)
+(* generator = "nMigen" *)
+module spblock512w64b8w_0(a, d, q, we, clk);
+       input [8:0] a;
+       input [63:0] d;
+       output [63:0] q;
+       input [7:0] we;
+       input clk;
+assign q = d;
+endmodule // SPBlock_512W64B8W
+

diff --git a/experiments9/non_generated/spblock512w64b8w_1.v b/experiments9/non_generated/spblock512w64b8w_1.v
new file mode 100644 (file)
index 0000000..c141da0
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w_1.v
@@ -0,0 +1,11 @@
+(* \nmigen.hierarchy  = "test_issuer.ti.sram4k_0.spblock512w64b8w_1" *)
+(* generator = "nMigen" *)
+module spblock512w64b8w_1(a, d, q, we, clk);
+       input [8:0] a;
+       input [63:0] d;
+       output [63:0] q;
+       input [7:0] we;
+       input clk;
+assign q = d;
+endmodule // SPBlock_512W64B8W
+

diff --git a/experiments9/non_generated/spblock512w64b8w_2.v b/experiments9/non_generated/spblock512w64b8w_2.v
new file mode 100644 (file)
index 0000000..29cf54b
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w_2.v
@@ -0,0 +1,11 @@
+(* \nmigen.hierarchy  = "test_issuer.ti.sram4k_0.spblock512w64b8w_2" *)
+(* generator = "nMigen" *)
+module spblock512w64b8w_2(a, d, q, we, clk);
+       input [8:0] a;
+       input [63:0] d;
+       output [63:0] q;
+       input [7:0] we;
+       input clk;
+assign q = d;
+endmodule // SPBlock_512W64B8W
+

diff --git a/experiments9/non_generated/spblock512w64b8w_3.v b/experiments9/non_generated/spblock512w64b8w_3.v
new file mode 100644 (file)
index 0000000..ec83783
--- /dev/null
+++ b/experiments9/non_generated/spblock512w64b8w_3.v
@@ -0,0 +1,11 @@
+(* \nmigen.hierarchy  = "test_issuer.ti.sram4k_0.spblock512w64b8w_3" *)
+(* generator = "nMigen" *)
+module spblock512w64b8w_3(a, d, q, we, clk);
+       input [8:0] a;
+       input [63:0] d;
+       output [63:0] q;
+       input [7:0] we;
+       input clk;
+assign q = d;
+endmodule // SPBlock_512W64B8W
+