add 2 PWMs (quick, easy to do)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 22 Sep 2020 21:47:02 +0000 (22:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 22 Sep 2020 21:47:02 +0000 (22:47 +0100)
src/soc/litex/florent/libresoc/ls180.py
src/soc/litex/florent/ls180soc.py

index bcf363b5289e168068ee7325b8c835f00b6572e1..ce99735ef424f7537899634edbba70afdcf752a0 100644 (file)
@@ -87,6 +87,8 @@ _io = [
         Misc("SLEWRATE=FAST"),
     ),
 
+    ("pwm", 0, Pins("P1"), IOStandard("LVCMOS33")),
+    ("pwm", 1, Pins("P2"), IOStandard("LVCMOS33")),
 ]
 
 if False:
index 4f4b3d24a6c7588448b28b4a2e88a468061e945c..877abf020f6d4e059b9ff6e6cedb68688024b11b 100755 (executable)
@@ -22,6 +22,7 @@ from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY
 
 from litex.soc.cores.gpio import GPIOInOut, GPIOIn, GPIOOut#, GPIOTristate
 from litex.soc.cores.spi import SPIMaster
+from litex.soc.cores.pwm import PWM
 
 from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
 
@@ -198,6 +199,13 @@ class LibreSoCSim(SoCCore):
         self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi)
         self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo)
 
+        # PWM
+        for i in range(2):
+            name = "pwm%d" % i
+            setattr(self.submodules, name, PWM(platform.request("pwm", i)))
+            self.add_csr(name)
+
+
         # Debug ---------------------------------------------------------------
         if not debug:
             return